migraphx: expose migraphx_bf16_enable, fp8_enable, int8_enable as direct config parameters

[zhihuidu-amd]

Problem

The MIGraphX execution provider in ORT 1.17+ accepts migraphx_bf16_enable,
migraphx_fp8_enable, and migraphx_int8_enable as ProviderOptions keys.
However, the Triton ONNX backend's MIGraphX parameter allowlist did not include
these keys. Passing them in config.pbtxt produced:

The existing precision_mode parameter handles these as a mutual-exclusion
enum ("FP16", "BF16", "FP8", "INT8"), but direct boolean keys allow
finer-grained control — for example, enabling BF16 compute with FP32 I/O
(migraphx_bf16_enable: true) without routing through the enum.

This is particularly relevant on CDNA3 / MI300X with ROCm ≥ 6.4.2 where
BF16 has the same matrix-engine throughput as FP16 but provides FP32 dynamic
range, avoiding overflow on large logits in ranking/recommendation models.

Also adds migraphx_mem_limit (already in ORT) to allow capping the GPU
memory arena from config.pbtxt.

Changes

src/onnxruntime.cc: add four else if branches after migraphx_exhaustive_tune:

• migraphx_bf16_enable — parsed as bool via ParseBoolValue
• migraphx_fp8_enable — parsed as bool via ParseBoolValue
• migraphx_int8_enable — parsed as bool via ParseBoolValue
• migraphx_mem_limit — parsed as unsigned long long

All follow the identical pattern established by migraphx_exhaustive_tune.

Example config.pbtxt usage

gpu_execution_accelerator [{
  name: "migraphx"
  parameters { key: "migraphx_bf16_enable"      value: "1"   }
  parameters { key: "migraphx_max_dynamic_batch" value: "256" }
}]

Tested on

MI300X (gfx942), ROCm 7.x, ORT 1.23.2, Triton Inference Server 25.x