Mini-Soc-Acc/mi_soc.py at main · AlexanderGSC/Mini-Soc-Acc · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc_core import SoCCore
from litex.soc.integration.builder import Builder
from litex.soc.interconnect.csr import *
from litex.soc.integration.common import get_mem_data
import numpy as np

# -----------------------------------------------------------------------------
# 1. IO - UART simulado
# -----------------------------------------------------------------------------
_io = [
    ("sys_clk", 0, Pins(1)),
    ("sys_rst", 0, Pins(1)),
    ("serial", 0,
        Subsignal("source_valid", Pins(1)),
        Subsignal("source_ready", Pins(1)),
        Subsignal("source_data",  Pins(8)),
        Subsignal("sink_valid",   Pins(1)),
        Subsignal("sink_ready",   Pins(1)),
        Subsignal("sink_data",    Pins(8)),
    ),
]

# Plataforma

class Platform(SimPlatform):
    default_clk_name   = "sys_clk"
    default_clk_period = 1000

    def __init__(self):
        SimPlatform.__init__(self, "SIM", _io)


# -----------------------------------------------------------------------------
# 3. Acelerador HW (CSR)
# -----------------------------------------------------------------------------
class Acelerador(Module, AutoCSR):
    def __init__(self):
        self.params_a  = CSRStorage(32)
        self.params_b  = CSRStorage(32)
        self.resultado = CSRStatus(32)

# -----------------------------------------------------------------------------
# 4. SoC principal
# -----------------------------------------------------------------------------

class MiSoC(SoCCore):
    def __init__(self):
        platform = Platform()
        sys_clk_freq = int(100e6)

        # Importante: uart_name coincide con el nombre del IO "serial"
        SoCCore.__init__(self, platform,
            cpu_type             = "vexriscv",
            clk_freq             = 1e6,
            ident                = "LiteX CPU Test SoC",
            uart_name            = "sim",
            ident_version        = True,
            integrated_rom_size  = 0x8000,
            cpu_reset_address    = 0x00000000, # Forzamos el reset a la ROM
            integrated_sram_size = 0x4000,
        )
        bin_data = np.fromfile("firmware/firmware.bin", dtype="uint32").tolist()
        self.add_ram("main_ram", origin=0x40000000, size=0x10000, contents=bin_data)
        self.add_constant("MAIN_RAM_NO_TEST")
        self.add_constant("MAIN_RAM_NO_INIT")
        #self.add_constant("ROM_BOOT_ADDRESS", 0x10000000)
        #self.add_rom("bios", origin=0x00000000, size=0x8000, contents=list(open("demo.bin", "rb").read()))
        self.submodules.crg = CRG(platform.request("sys_clk"), platform.request("sys_rst"))
        self.add_constant("UART_POLLING")
        # Acelerador
        self.submodules.mult_hw = Acelerador()
        self.add_csr("mult_hw")

        # Instancia del módulo Verilog
        self.specials += Instance("MultiplicadorVerilog",
            i_clk = ClockSignal("sys"),
            i_a   = self.mult_hw.params_a.storage,
            i_b   = self.mult_hw.params_b.storage,
            o_resultado = self.mult_hw.resultado.status
        )
        platform.add_source("multiplicador.v")

# -----------------------------------------------------------------------------
# 5. Main: build y sim
# -----------------------------------------------------------------------------
if __name__ == "__main__":
    soc = MiSoC()
    sim_config = SimConfig()

    # 2. Añadimos un "clocker" (generador de reloj)
    # El nombre "sys_clk" debe coincidir con el nombre en tu _io
    sim_config.add_module("serial2console", "serial")
    sim_config.add_clocker("sys_clk", freq_hz=int(1e6))

    builder = Builder(soc, output_dir="build_soc", csr_csv="test/csr.csv")
    builder.build(build_name="sim", sim_config=sim_config, trace=True,opt_level   = "O0",)