ANDROID: riscv: dts: spacemit: add nodes for new K1 peripherals

Add device-tree nodes describing the K1 peripherals brought in by the
preceding driver commits:

* dram_range0 / dram_range1 (spacemit-dram-bus): per-master DRAM
  dma-ranges. dram_range0 limits USB/SDH/Ethernet to the first 2GB;
  dram_range1 lets the VPU/GPU/DPU access full DDR via the
  interconnect framework.
* ddraxi_mon (spacemit,ddraxi-mon): DDR AXI bandwidth monitor at
  0xc0058500.
* combphy (spacemit,k1x-combphy): USB3+PCIe combo PHY at 0xc0b10000.
  Shared reset with PCIe0 (RESET_PCIE0_GLOBAL).
* reboot_handler (spacemit,k1x-reboot): SoC boot-mode register at
  0xd4282f90 used to select next-boot mode before warm reset.
* efuse / efuse_bank7 (spacemit,k1-efuse): on-die fuse banks at
  0xf0702800 wrapped under simple-mfd.
* k1-bananapi-f3.dts, k1-x-peripherals.dtsi, k1-hdmi.dtsi: enable
  the new nodes for the BananaPi F3 and wire the HDMI/USB/PCIe
  consumers to them.

Change-Id: Ia9059ee7a914b042ed1c6aec12bdf1362b6e1f35
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>

Author: glaroque

arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts

@@ -817,3 +817,19 @@
 		};
 	};
 };
+
+&reboot_handler {
+	status = "okay";
+};
+
+&efuse {
+	status = "okay";
+};
+
+&efuse_bank7 {
+	status = "okay";
+};
+
+&socinfo {
+	status = "okay";
+};

arch/riscv/boot/dts/spacemit/k1-hdmi.dtsi

@@ -12,6 +12,8 @@
 		compatible = "spacemit,saturn-hdmi";
 		reg = <0 0xc0440000 0 0x2A000>;
 		ports = <&dpu_online2_hdmi>;
+		interconnects = <&dram_range1>;
+		interconnect-names = "dma-mem";
 	};
 
 	dpu_online2_hdmi: port@c0440000 {

arch/riscv/boot/dts/spacemit/k1-x-peripherals.dtsi

@@ -6,6 +6,9 @@
  * Adapted for Android kernel syscon clock/reset references
  */
 
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/spacemit-k1x-power.h>
+
 /* ============================================================
  * USB Subsystem
  * ============================================================ */
@@ -140,7 +143,12 @@
 		clocks = <&syscon_apmu CLK_USB30>;
 		clock-names = "usbdrd30";
 		usb-phy = <&usb2phy>;
+		phys = <&combphy PHY_TYPE_USB3>;
+		phy-names = "usb3-phy";
+		interconnects = <&dram_range0>;
+		interconnect-names = "dma-mem";
 		interrupts = <149>;
+		reset-on-resume;
 		ranges;
 		status = "disabled";
 
@@ -150,9 +158,13 @@
 			interrupts = <125>;
 			dr_mode = "host";
 			phy_type = "utmi";
+			snps,hsphy_interface = "utmi";
 			snps,dis_enblslpm_quirk;
 			snps,dis_u2_susphy_quirk;
 			snps,dis_u3_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
 		};
 	};
 

arch/riscv/boot/dts/spacemit/k1.dtsi

@@ -347,6 +347,55 @@
 		dma-noncoherent;
 		ranges;
 
+		/* DRAM mapping for USB/SDH/Ethernet: first 2GB only. */
+		dram_range0: dram_range@0 {
+			compatible = "spacemit-dram-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+			#interconnect-cells = <0>;
+			status = "okay";
+		};
+
+		/* DRAM mapping for VPU/GPU/DPU access. Used by the interconnect
+		 * framework so the DPU can access full DDR (>2GB).
+		 * Ported from vendor BSP linux-6.6 k1-x.dtsi.
+		 */
+		dram_range1: dram_range@1 {
+			compatible = "spacemit-dram-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
+				     <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
+			#interconnect-cells = <0>;
+			status = "okay";
+		};
+
+		/* DDR AXI bandwidth monitor */
+		ddraxi_mon: ddraxi_mon@c0058500 {
+			compatible = "spacemit,ddraxi-mon";
+			reg = <0x0 0xc0058500 0x0 0x80>;
+			status = "okay";
+		};
+
+		/* USB3 + PCIe combo PHY (required for xHCI USB 3.0 init).
+		 * The reset called RESET_COMBO_PHY upstream (id 76) maps to the
+		 * exact same APMU register bit as RESET_PCIE0_GLOBAL (id 26) in
+		 * the AOSP syscon-apmu reset table:
+		 *     [RESET_PCIE0_GLOBAL] = APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0
+		 * The combphy is shared between USB3 and PCIe0, hence the same reset.
+		 */
+		combphy: phy@c0b10000 {
+			compatible = "spacemit,k1x-combphy";
+			reg = <0x0 0xc0b10000 0x0 0x800>,
+			      <0x0 0xd4282910 0x0 0x400>;
+			reg-names = "puphy", "phy_sel";
+			resets = <&syscon_apmu RESET_PCIE0_GLOBAL>;
+			reset-names = "phy_rst";
+			#phy-cells = <1>;
+			status = "okay";
+		};
+
 		syscon_rcpu: system-controller@c0880000 {
 			compatible = "spacemit,k1-syscon-rcpu";
 			reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -1113,6 +1162,66 @@
 
 	thermal_zones: thermal-zones {
 	};
+
+	reboot_handler: handler@d4282f90 {
+		compatible = "spacemit,k1x-reboot";
+		reg = <0x0 0xd4282f90 0x0 0x4>;
+		status = "disabled";
+	};
+
+	efuse: fuse@f0702800 {
+		compatible = "simple-mfd";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0xf0702800 0x400>;
+		status = "disabled";
+
+		efuse_bank7: efuse_bank@7 {
+			compatible = "spacemit,k1-efuse";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x190 0x20>;
+			resets = <&syscon_apmu RESET_AES>;
+			reset-names = "aes_reset";
+			clocks = <&syscon_apmu CLK_AES>;
+			clock-names = "aes_core";
+			status = "disabled";
+
+			soc_die_id: bank7_die_id@11 {
+				reg = <0x11 3>;
+				bits = <3 16>;
+			};
+
+			soc_ver_id: bank7_ver_id@1f {
+				reg = <0x1F 1>;
+				bits = <6 2>;
+			};
+
+			soc_pack_id: bank7_pack_id@16 {
+				reg = <0x16 2>;
+				bits = <6 9>;
+			};
+
+			soc_svt_dro: bank7_svt_dro@15 {
+				reg = <0x15 2>;
+				bits = <5 9>;
+			};
+
+			soc_chip_id: bank7_chip_id@17 {
+				reg = <0x17 8>;
+				bits = <7 55>;
+			};
+		};
+	};
+
+	socinfo: socinfo {
+		compatible = "spacemit,socinfo-k1x";
+		nvmem-cells = <&soc_die_id>, <&soc_ver_id>, <&soc_pack_id>,
+			      <&soc_svt_dro>, <&soc_chip_id>;
+		nvmem-cell-names = "soc_die_id", "soc_ver_id", "soc_pack_id",
+				   "soc_svt_dro", "soc_chip_id";
+		status = "disabled";
+	};
 };
 
 /* Include additional peripherals (USB, Camera) for K1-X SoC */