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| 1 | +/* |
| 2 | + * Copyright (c) Meta Platforms, Inc. and affiliates. |
| 3 | + * All rights reserved. |
| 4 | + * |
| 5 | + * This source code is licensed under the BSD-style license found in the |
| 6 | + * LICENSE file in the root directory of this source tree. |
| 7 | + */ |
| 8 | + |
| 9 | +#pragma once |
| 10 | + |
| 11 | +#include <cstdint> |
| 12 | + |
| 13 | +namespace executorch::backends::webgpu { |
| 14 | + |
| 15 | +// @generated from q4gsw_linear_gemm_shmem.wgsl - DO NOT EDIT. |
| 16 | +// wgsl-sha256: 0a1219d3b6781315a21066089fca3f92235587e8af8eb734185f35ea4bfc8a52 |
| 17 | +inline constexpr const char* kQ4gswLinearGemmShmemWGSL = R"( |
| 18 | +@group(0) @binding(0) var<storage, read_write> t_out: array<f32>; |
| 19 | +@group(0) @binding(1) var<storage, read> t_input: array<f32>; |
| 20 | +@group(0) @binding(2) var<storage, read> t_weight: array<u32>; |
| 21 | +@group(0) @binding(3) var<storage, read> t_scales: array<f32>; |
| 22 | +@group(0) @binding(4) var<storage, read> t_bias: array<f32>; |
| 23 | +
|
| 24 | +struct Params { |
| 25 | + M: u32, |
| 26 | + N: u32, |
| 27 | + K: u32, |
| 28 | + K_packed: u32, |
| 29 | + group_size: u32, |
| 30 | + padded_N: u32, |
| 31 | + has_bias: u32, |
| 32 | + _pad: u32, |
| 33 | +} |
| 34 | +@group(0) @binding(5) var<uniform> params: Params; |
| 35 | +
|
| 36 | +override wg_size: u32 = 64u; |
| 37 | +
|
| 38 | +// Shmem-staged tiled GEMM (M>1): dequant weight into shmem once per K-tile. |
| 39 | +const WG_M: u32 = 32u; // output rows per workgroup |
| 40 | +const WG_N: u32 = 32u; // output cols per workgroup |
| 41 | +const TM: u32 = 4u; // rows per thread |
| 42 | +const TN: u32 = 4u; // cols per thread |
| 43 | +const TK: u32 = 16u; // K-tile depth |
| 44 | +const THREADS: u32 = 64u; // 8x8 thread grid (must equal wg_size) |
| 45 | +
|
| 46 | +var<workgroup> in_sh: array<f32, 512>; // WG_M * TK = 32 * 16 |
| 47 | +var<workgroup> w_sh: array<f32, 512>; // TK * WG_N = 16 * 32 |
| 48 | +
|
| 49 | +@compute @workgroup_size(wg_size, 1, 1) |
| 50 | +fn main(@builtin(workgroup_id) wid: vec3<u32>, |
| 51 | + @builtin(local_invocation_index) lid: u32) { |
| 52 | + let nct = (params.N + WG_N - 1u) / WG_N; // output-col tiles |
| 53 | + let tile_row = wid.x / nct; |
| 54 | + let tile_col = wid.x % nct; |
| 55 | + let m_base = tile_row * WG_M; // first output row of this WG's tile |
| 56 | + let n_base = tile_col * WG_N; // first output col of this WG's tile |
| 57 | +
|
| 58 | + // This thread's 4x4 sub-tile origin within the 32x32 WG tile (8x8 thread grid). |
| 59 | + let tr = lid / 8u; // thread row in [0,8) |
| 60 | + let tc = lid % 8u; // thread col in [0,8) |
| 61 | + let m_thread = m_base + tr * TM; |
| 62 | + let n_thread = n_base + tc * TN; |
| 63 | +
|
| 64 | + var acc: array<f32, 16>; // TM * TN |
| 65 | + for (var i: u32 = 0u; i < TM * TN; i = i + 1u) { |
| 66 | + acc[i] = 0.0; |
| 67 | + } |
| 68 | +
|
| 69 | + var k0: u32 = 0u; |
| 70 | + loop { |
| 71 | + if (k0 >= params.K) { break; } |
| 72 | +
|
| 73 | + // (a) Stage the 32xTK input block into shmem; 64 threads x 8 elems; OOB->0. |
| 74 | + for (var t: u32 = lid; t < WG_M * TK; t = t + THREADS) { |
| 75 | + let r = t / TK; // row within the WG tile [0,32) |
| 76 | + let c = t % TK; // col within the K-tile [0,16) |
| 77 | + let m = m_base + r; |
| 78 | + let k = k0 + c; |
| 79 | + var v: f32 = 0.0; |
| 80 | + if (m < params.M && k < params.K) { |
| 81 | + v = t_input[m * params.K + k]; |
| 82 | + } |
| 83 | + in_sh[t] = v; |
| 84 | + } |
| 85 | +
|
| 86 | + // (b) Dequant the TKx32 weight block into shmem once; dq = (nibble-8)*scale. |
| 87 | + for (var t: u32 = lid; t < TK * WG_N; t = t + THREADS) { |
| 88 | + let kk = t / WG_N; // k within the K-tile [0,16) |
| 89 | + let nn = t % WG_N; // col within the WG tile [0,32) |
| 90 | + let n = n_base + nn; |
| 91 | + let k = k0 + kk; |
| 92 | + var dq: f32 = 0.0; |
| 93 | + if (n < params.N && k < params.K) { |
| 94 | + let byte_idx = n * params.K_packed + (k >> 1u); |
| 95 | + let word = t_weight[byte_idx >> 2u]; |
| 96 | + let b = (word >> ((byte_idx & 3u) * 8u)) & 0xFFu; |
| 97 | + var nib: u32; |
| 98 | + if ((k & 1u) == 0u) { |
| 99 | + nib = b & 0x0Fu; // even k -> low nibble |
| 100 | + } else { |
| 101 | + nib = (b >> 4u) & 0x0Fu; // odd k -> high nibble |
| 102 | + } |
| 103 | + let q = f32(i32(nib) - 8); // +8-shifted on pack; recover [-8,7] |
| 104 | + dq = q * t_scales[(k / params.group_size) * params.padded_N + n]; |
| 105 | + } |
| 106 | + w_sh[t] = dq; |
| 107 | + } |
| 108 | +
|
| 109 | + workgroupBarrier(); |
| 110 | +
|
| 111 | + // Accumulate this thread's 4x4 tile from shared memory. |
| 112 | + let k_lim = min(TK, params.K - k0); |
| 113 | + for (var kk: u32 = 0u; kk < k_lim; kk = kk + 1u) { |
| 114 | + var a: array<f32, 4>; |
| 115 | + for (var ml: u32 = 0u; ml < TM; ml = ml + 1u) { |
| 116 | + a[ml] = in_sh[(tr * TM + ml) * TK + kk]; |
| 117 | + } |
| 118 | + for (var nl: u32 = 0u; nl < TN; nl = nl + 1u) { |
| 119 | + let wv = w_sh[kk * WG_N + (tc * TN + nl)]; |
| 120 | + for (var ml: u32 = 0u; ml < TM; ml = ml + 1u) { |
| 121 | + acc[ml * TN + nl] = acc[ml * TN + nl] + a[ml] * wv; |
| 122 | + } |
| 123 | + } |
| 124 | + } |
| 125 | +
|
| 126 | + workgroupBarrier(); |
| 127 | + k0 = k0 + TK; |
| 128 | + } |
| 129 | +
|
| 130 | + // Write the 4x4 register tile out (bounds-guarded; bias added per column). |
| 131 | + for (var ml: u32 = 0u; ml < TM; ml = ml + 1u) { |
| 132 | + let m = m_thread + ml; |
| 133 | + for (var nl: u32 = 0u; nl < TN; nl = nl + 1u) { |
| 134 | + let n = n_thread + nl; |
| 135 | + if (m < params.M && n < params.N) { |
| 136 | + var v = acc[ml * TN + nl]; |
| 137 | + if (params.has_bias != 0u) { |
| 138 | + v = v + t_bias[n]; |
| 139 | + } |
| 140 | + t_out[m * params.N + n] = v; |
| 141 | + } |
| 142 | + } |
| 143 | + } |
| 144 | +} |
| 145 | +)"; |
| 146 | + |
| 147 | +inline constexpr uint32_t kQ4gswLinearGemmShmemWorkgroupSizeX = 64; |
| 148 | +inline constexpr uint32_t kQ4gswLinearGemmShmemWorkgroupSizeY = 1; |
| 149 | +inline constexpr uint32_t kQ4gswLinearGemmShmemWorkgroupSizeZ = 1; |
| 150 | + |
| 151 | +} // namespace executorch::backends::webgpu |
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