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Arm backend: Fix Cortex-M55 CPU cycle measurements (pytorch#21833)
The affected GCC Arm Cortex-M55 build defines __ARM_ARCH_8M_MAIN__, so the existing __ARM_ARCH_8_1M_MAIN__ guard excludes PMU initialization and counter reads. Consequently, inference runtime is always reported as zero CPU cycles on the Cortex-M55 FPGA. Guard PMU access using the CMSIS __PMU_PRESENT device capability. This describes the hardware requirement directly and avoids relying on architecture macros or a list of specific processor names. cc @digantdesai @freddan80 @per @zingo @oscarandersson8218 @Sebastian-Larsson @robell @rascani Signed-off-by: Måns Nilsson <mans.nilsson@arm.com>
1 parent 09ba075 commit 79e3eae

2 files changed

Lines changed: 5 additions & 5 deletions

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‎examples/arm/executor_runner/arm_executor_runner.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ unsigned char __attribute__((
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constexpr size_t FAST_MEMORY_REGION_INDEX = 2;
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[[maybe_unused]] void et_pal_init(void) {
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#if defined(__ARM_ARCH_8_1M_MAIN__)
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#if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U)
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// Armv8.1-M Mainline cores (M55, M85) have the optional PMU extension.
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// Pre-Armv8.1-M cores lack ARM_PMU_*; et_pal_current_ticks() returns 0.
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ARM_PMU_Enable();
@@ -327,7 +327,7 @@ constexpr size_t FAST_MEMORY_REGION_INDEX = 2;
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}
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[[maybe_unused]] et_timestamp_t et_pal_current_ticks(void) {
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#if defined(__ARM_ARCH_8_1M_MAIN__)
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#if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U)
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return ARM_PMU_Get_CCNTR();
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#else
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return 0;

‎examples/arm/executor_runner/arm_perf_monitor.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
/* Copyright 2024-2025 Arm Limited and/or its affiliates.
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/* Copyright 2024-2026 Arm Limited and/or its affiliates.
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*
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* This source code is licensed under the BSD-style license found in the
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* LICENSE file in the root directory of this source tree.
@@ -18,7 +18,7 @@ namespace {
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// Returns the Armv8.1-M PMU cycle counter; 0 on cores without it.
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static inline uint64_t arm_pmu_cycles() {
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#if defined(__ARM_ARCH_8_1M_MAIN__)
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#if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U)
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return ARM_PMU_Get_CCNTR();
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#else
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return 0;
@@ -139,7 +139,7 @@ void StartMeasurements() {
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}
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void StopMeasurements(int num_inferences) {
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#if defined(__ARM_ARCH_8_1M_MAIN__)
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#if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U)
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ARM_PMU_CNTR_Disable(
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PMU_CNTENCLR_CCNTR_ENABLE_Msk | PMU_CNTENCLR_CNT0_ENABLE_Msk |
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PMU_CNTENCLR_CNT1_ENABLE_Msk);

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