[CPU] Fix FP16/BF16 convolution and layer normalization (pytorch#23153)

### Summary

Portable convolution accumulates FP16/BF16 products in the output dtype,
so long reductions lose contributions: summing 3072 ones can return 2048
in FP16 or 256 in BF16. Both ordinary and transposed convolution now
accumulate products and bias in FP32 and narrow once per output.
Transposed convolution visits bounded input/kernel ranges for 8x32
output tiles and reuses weights across contributing inputs. Each tile
uses a fixed stack buffer (1 KiB for FP32 accumulators), with one cast
per output after bias. The tiled helper and dtype wrapper stay separate
from scalar-type dispatch to preserve ordinary/depthwise convolution
performance.

Optimized layer normalization routes FP16/BF16 through the shared scalar
helper because RowwiseMoments does not implement their vector loads. The
helper now uses corrected two-pass moments to prevent cancellation and
NaNs on large-mean rows, accumulating in FP32 for Half/BFloat16/Float
and FP64 for Double. Both kernel wrappers preserve epsilon in compute
precision. This also fixes the existing portable and small-row FP32/FP64
cases. The large-row FP32/FP64 SIMD path is unchanged; reduced-precision
SIMD support remains a follow-up in pytorch#23159.

This PR contains only CPU kernel fixes and unit tests. It is a
prerequisite for the BF16 CPU path in pytorch#23152.

### Test plan

Added FP16/BF16 tests for long ordinary and transposed convolution
reductions, mixed FP32 bias, and grouped transposed convolution with
stride, dilation, output padding, and both layouts. The grouped tests
use 1024 input channels per group and match both the PyTorch FP32
reference and native FP16/BF16 results. The existing FP32 geometry case
remains a regression guard.

Built the same test sources against the original kernels at 00e5030
and the fixed kernels. Before: eight convolution tests and both
reduced-precision optimized layer-normalization tests fail. After: the
convolution, portable layer-normalization, and optimized
layer-normalization suites pass. Also built the layer-normalization
suite with USE_ATEN_LIB: BFloat16LargeRows fails with the original
exact-mean assertion and passes with the tolerant assertion. The current
convolution suite passes 29 tests with one expected skip. Four added
geometry tests cover coprime and shared-factor stride/dilation, full and
partial tiles, strides larger than a tile, and both layouts; all four
also pass in ATen mode.

Compared 1,711 convolution cases against PyTorch, including 512
generated from the FACTO convolution specification and 768 additional
stride/dilation cases. All numerical checks and UBSan checks pass.
Reduced-precision references run PyTorch convolution in FP32 on
already-rounded inputs and cast the result once. All outputs are bitwise
identical to the previous PR head, 115d394. The earlier Nemotron BF16
production regression passes across all four presets.

Added six layer-normalization regressions covering large-mean and
constant rows in all four floating dtypes, odd tails, affine
normalization, and tiny epsilon values. Each fails against both portable
and optimized kernels at the previous PR head, 21a4ad2. With the fix,
each native suite passes 16 tests with one expected skip; the ATen suite
passes 14 with three expected skips. Both native suites also pass under
UBSan.

An 800-case numerical grid covers random, large-mean, and constant
inputs, widths from 1 to 4096, all combinations of optional weight/bias,
and tiny epsilon. Scalar results match a PyTorch FP64 reference within
dtype-appropriate tolerances, with no unexpected NaNs or infinities.
Existing optimized FP32/FP64 SIMD outputs remain bitwise identical to
21a4ad2. The grid also passes under UBSan. These checks ran on macOS
arm64.

`lintrunner` and `git diff --check` pass. Supplemental test harnesses
and results remain local.

Authored with AI assistance from OpenAI Codex.

Author: mergennachin

kernels/optimized/cpu/op_native_layer_norm.cpp

@@ -9,6 +9,7 @@
 #include <executorch/runtime/kernel/kernel_includes.h>
 #include <cmath>
 #include <tuple>
+#include <type_traits>
 
 #include <ATen/cpu/vec/functional.h>
 #include <ATen/cpu/vec/vec.h>
@@ -29,7 +30,7 @@ void layer_norm(
     IntArrayRef normalized_shape,
     const optional<Tensor>& weight,
     const optional<Tensor>& bias,
-    CTYPE eps,
+    double eps,
     Tensor& out,
     Tensor& mean,
     Tensor& rstd) {
@@ -72,11 +73,10 @@ void layer_norm(
   const bool gamma_null = gamma_data == nullptr;
   const bool beta_null = beta_data == nullptr;
 
-  // For small normalized dimensions, fall back to the portable scalar
-  // implementation since SIMD vectorization setup/tail-handling overhead
-  // exceeds the benefit for small N.
+  // RowwiseMoments lacks reduced-precision vector loads. The scalar path also
+  // avoids SIMD setup/tail-handling overhead for small normalized dimensions.
   constexpr size_t kSmallNThreshold = 256;
-  if (N < kSmallNThreshold) {
+  if (N < kSmallNThreshold || !std::is_same_v<CTYPE, acc_t<CTYPE>>) {
     layer_norm_scalar<CTYPE>(
         input_data,
         gamma_data,
@@ -97,7 +97,8 @@ void layer_norm(
     acc_t<CTYPE> mean_val;
     acc_t<CTYPE> rstd_val;
     std::tie(mean_val, rstd_val) = RowwiseMoments(src_ptr, N);
-    rstd_val = CTYPE(1) / std::sqrt(rstd_val + eps);
+    rstd_val =
+        acc_t<CTYPE>(1) / std::sqrt(rstd_val + static_cast<acc_t<CTYPE>>(eps));
 
     const acc_t<CTYPE> scale = rstd_val;
     const acc_t<CTYPE> offset = -rstd_val * mean_val;