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[cuda backend] support multi-SM AOTI PTEs (pytorch#22198)
### Summary
Add one current `ETCUDAFQN0` metadata format that stores target-specific
CUDA AOTI shared libraries with one shared FQN weight manifest. At
runtime, CUDA first selects an exact-SM regular variant. If no exact
regular variant exists, it may use the PTX from one explicitly
designated fallback PTE when that PTX is compatible with the current
GPU. The fallback is no longer inferred from the lowest regular target
SM.
Add a PTE/PTD merge tool with two input classes:
- One or more regular PTEs provide exact-SM native variants. Their
merged metadata sets `ptx_compute=0`, so they are never considered as
PTX fallbacks. Regular exports should use
`CompileSpec("cuda_include_ptx", b"OFF")` to avoid embedding redundant
PTX.
- At most one fallback PTE provides the PTX-capable variant. It is
marked `fallback_only`, is never selected as an exact native variant,
and is considered only when the merged PTE has no regular variant for
the current SM.
The merge validates the ExecuTorch program, CUDA delegate layout,
non-CUDA named data, weight metadata, and streamed PTD weight hashes.
CUDA PTE merging is NVIDIA-only and explicitly rejects ROCm.
### Merged artifact layout
For an A100 (`sm80`) regular export, an RTX 5090 (`sm120`) regular
export, and one PTX fallback export, the merged artifact is structured
as follows:
```text
merged.pte
├── program and CUDA delegates
│ └── `ETCUDAFQN0` CUDA variant metadata (per delegate)
│ ├── regular: target_sm=80, ptx_compute=0 -> sm80 source SO key
│ ├── regular: target_sm=120, ptx_compute=0 -> sm120 source SO key
│ └── fallback_only: target_sm=<source SM>,
│ ptx_compute=<fallback compute capability> -> fallback source SO key
├── named data
│ ├── sm80 source SO key -> actual AOTI SO containing the prebuilt sm80 cubin
│ ├── sm120 source SO key -> actual AOTI SO containing the prebuilt sm120 cubin
│ └── fallback source SO key -> actual PTX-bearing fallback AOTI SO
└── one shared FQN weight manifest
merged.ptd
└── shared external tensor data reused from the regular base export
```
The tool copies each AOTI SO atomically rather than rewriting its
ELF/fatbin. The regular/fallback distinction is encoded in the merged
metadata: only regular variants participate in exact-SM native
selection, while the fallback SO contributes PTX only to fallback
selection. After merging, the CLI prints a provenance table mapping
every stored SM cubin and the fallback PTX entry to its source PTE.
This PR was authored with OpenAI Codex.
### Test plan
The primary validation is a real cross-hardware CUDA CI pipeline
spanning A100 (`sm80`) and A10G (`sm86`):
1. Export an A100 native PTE and an A10G native PTE independently on
their respective GPUs, both with PTX disabled and isolated Inductor
caches.
2. Export a separate PTX fallback PTE on A100 with the A10G
shared-memory constraint.
3. Verify byte-for-byte that the A100 native PTD, A10G native PTD,
fallback PTD, and final merged PTD are identical.
4. On A10G, verify the A10G native PTE succeeds, the A100 native-only
PTE is rejected with no compatible native/PTX variant, and the merged
PTE succeeds.
5. On A100, verify the A100 native PTE succeeds, the A10G native-only
PTE is rejected with no compatible native/PTX variant, and the same
merged PTE succeeds.
Additional Python coverage exercises the single `ETCUDAFQN0` metadata
format, untargeted ROCm metadata, explicit fallback-only encoding,
PTE/PTD merging, shared-weight validation, duplicate regular SM
rejection, provenance reporting, and ROCm merge rejection. C++ coverage
exercises metadata parsing, exact regular selection, PTX fallback
selection, incompatibility, and duplicate targets.
Locally ran the 17 targeted CUDA metadata/merge tests, Python
lint/format checks, workflow YAML parsing, and `git diff --check`.1 parent 75c2b30 commit eadb4c3
15 files changed
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