|
| 1 | +/* |
| 2 | + Copyright (c) 2020, GigaDevice Semiconductor Inc. |
| 3 | +
|
| 4 | + Redistribution and use in source and binary forms, with or without modification, |
| 5 | +are permitted provided that the following conditions are met: |
| 6 | +
|
| 7 | + 1. Redistributions of source code must retain the above copyright notice, this |
| 8 | + list of conditions and the following disclaimer. |
| 9 | + 2. Redistributions in binary form must reproduce the above copyright notice, |
| 10 | + this list of conditions and the following disclaimer in the documentation |
| 11 | + and/or other materials provided with the distribution. |
| 12 | + 3. Neither the name of the copyright holder nor the names of its contributors |
| 13 | + may be used to endorse or promote products derived from this software without |
| 14 | + specific prior written permission. |
| 15 | +
|
| 16 | + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 18 | +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 19 | +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
| 20 | +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 21 | +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 22 | +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 24 | +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
| 25 | +OF SUCH DAMAGE. |
| 26 | +*/ |
| 27 | + |
| 28 | +#include "PeripheralPins.h" |
| 29 | +#include "gd32xxyy.h" |
| 30 | + |
| 31 | +/* void pin_function(PinName pin, int function); |
| 32 | + configure the speed, mode,and remap function of pins |
| 33 | + the parameter function contains the configuration information,show as below |
| 34 | + bit 0:2 gpio mode |
| 35 | + bit 3:8 remap |
| 36 | + bit 9:10 gpio speed |
| 37 | + bit 11:15 adc /timer channel |
| 38 | +*/ |
| 39 | +const int GD_GPIO_PULL_UP_DOWN[] = { |
| 40 | + GPIO_PUPD_NONE, /* 0 */ |
| 41 | + GPIO_PUPD_PULLUP, /* 1 */ |
| 42 | + GPIO_PUPD_PULLDOWN, /* 2 */ |
| 43 | +}; |
| 44 | + |
| 45 | +const int GD_GPIO_OUTPUT_MODE[] = { |
| 46 | + GPIO_OTYPE_PP, /* 0 */ |
| 47 | + GPIO_OTYPE_OD, /* 1 */ |
| 48 | +}; |
| 49 | + |
| 50 | +const int GD_GPIO_AF[] = { |
| 51 | + GPIO_AF_0, /* 0 */ |
| 52 | + GPIO_AF_1, /* 1 */ |
| 53 | + GPIO_AF_2, /* 2 */ |
| 54 | + GPIO_AF_3, /* 3 */ |
| 55 | + GPIO_AF_4, /* 4 */ |
| 56 | + GPIO_AF_5, /* 5 */ |
| 57 | + GPIO_AF_6, /* 6 */ |
| 58 | +}; |
| 59 | + |
| 60 | +/* pin descriptions only reference the index in the array, so |
| 61 | + * to get e.g. AF11 one must give it index = 9. provide |
| 62 | + * convenience macros here. |
| 63 | + * for all other arrays, the value is also equivalent to the index, |
| 64 | + * so there doesn't need to be anything done more. |
| 65 | + */ |
| 66 | +#define IND_GPIO_AF_0 0 |
| 67 | +#define IND_GPIO_AF_1 1 |
| 68 | +#define IND_GPIO_AF_2 2 |
| 69 | +#define IND_GPIO_AF_3 3 |
| 70 | +#define IND_GPIO_AF_4 4 |
| 71 | +#define IND_GPIO_AF_5 5 |
| 72 | +#define IND_GPIO_AF_6 6 |
| 73 | +#define IND_GPIO_AF_7 7 |
| 74 | +#define IND_GPIO_AF_9 8 |
| 75 | +#define IND_GPIO_AF_11 9 |
| 76 | + |
| 77 | +/* GPIO MODE */ |
| 78 | +const int GD_GPIO_MODE[] = { |
| 79 | + GPIO_MODE_INPUT, /* 0 */ |
| 80 | + GPIO_MODE_OUTPUT, /* 1 */ |
| 81 | + GPIO_MODE_AF, /* 2 */ |
| 82 | + GPIO_MODE_ANALOG, /* 3 */ |
| 83 | +}; |
| 84 | + |
| 85 | +/* GPIO SPEED */ |
| 86 | +const int GD_GPIO_SPEED[] = { |
| 87 | + GPIO_OSPEED_2MHZ, /* 0 */ |
| 88 | + GPIO_OSPEED_10MHZ, /* 1 */ |
| 89 | + 0, /* 2 (unused) */ |
| 90 | + GPIO_OSPEED_50MHZ, /* 3 */ |
| 91 | +}; |
| 92 | + |
| 93 | +/* ADC PinMap */ |
| 94 | +const PinMap PinMap_ADC[] = { |
| 95 | + {PORTA_0, ADC, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC_IN0 */ |
| 96 | + {PORTA_1, ADC, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC_IN1 */ |
| 97 | + {PORTA_2, ADC, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC_IN2 */ |
| 98 | + {PORTA_3, ADC, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC_IN3 */ |
| 99 | + {PORTA_4, ADC, GD_PIN_FUNC_ANALOG_CH(4)}, /* ADC_IN4 */ |
| 100 | + {PORTA_5, ADC, GD_PIN_FUNC_ANALOG_CH(5)}, /* ADC_IN5 */ |
| 101 | + {PORTA_6, ADC, GD_PIN_FUNC_ANALOG_CH(6)}, /* ADC_IN6 */ |
| 102 | + {PORTA_7, ADC, GD_PIN_FUNC_ANALOG_CH(7)}, /* ADC_IN7 */ |
| 103 | + {PORTB_0, ADC, GD_PIN_FUNC_ANALOG_CH(8)}, /* ADC_IN8 */ |
| 104 | + {PORTB_1, ADC, GD_PIN_FUNC_ANALOG_CH(9)}, /* ADC_IN9 */ |
| 105 | + {ADC_TEMP, ADC, GD_PIN_FUNC_ANALOG_CH(16)}, /* ADC_IN16 */ |
| 106 | + {ADC_VREF, ADC, GD_PIN_FUNC_ANALOG_CH(17)}, /* ADC_IN17 */ |
| 107 | + {NC, NC, 0} |
| 108 | +}; |
| 109 | + |
| 110 | +/* DAC PinMap */ |
| 111 | +const PinMap PinMap_DAC[] = { |
| 112 | + {NC, NC, 0} |
| 113 | +}; |
| 114 | + |
| 115 | +/* I2C_SDA PinMap */ |
| 116 | +const PinMap PinMap_I2C_SDA[] = { |
| 117 | + {PORTA_1, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* I2C1_SDA */ |
| 118 | + {PORTA_10, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* I2C0_SDA */ |
| 119 | + {PORTA_12, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_5)}, /* I2C1_SDA */ |
| 120 | + {PORTB_7, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SDA */ |
| 121 | + {PORTB_9, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SDA */ |
| 122 | + {PORTB_14, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_5)}, /* I2C1_SDA */ |
| 123 | + {PORTF_0, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SDA */ |
| 124 | + {PORTF_7, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_0)}, /* I2C0_SDA( */ |
| 125 | + {PORTF_7, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_0)}, /* I2C1_SDA */ |
| 126 | + {NC, NC, 0} |
| 127 | +}; |
| 128 | + |
| 129 | +/* I2C_SCL PinMap */ |
| 130 | +const PinMap PinMap_I2C_SCL[] = { |
| 131 | + {PORTA_0, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* I2C1_SCL */ |
| 132 | + {PORTA_9, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* I2C0_SCL */ |
| 133 | + {PORTA_11, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_5)}, /* I2C1_SCL */ |
| 134 | + {PORTB_6, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SCL */ |
| 135 | + {PORTB_8, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SCL */ |
| 136 | + {PORTB_13, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_5)}, /* I2C1_SCL */ |
| 137 | + {PORTF_1, I2C0, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* I2C0_SCL */ |
| 138 | + {PORTF_6, I2C1, GD_PIN_FUNCTION4(PIN_MODE_AF, PIN_OTYPE_OD, PIN_PUPD_PULLUP, IND_GPIO_AF_0)}, /* I2C1_SCL */ |
| 139 | + {NC, NC, 0} |
| 140 | +}; |
| 141 | + |
| 142 | +/* PWM PinMap */ |
| 143 | +const PinMap PinMap_PWM[] = { |
| 144 | + {PORTA_1, TIMER14, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_5)}, /* TIMER14_CH0_ON */ |
| 145 | + {PORTA_2, TIMER14, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_0)}, /* TIMER14_CH0 */ |
| 146 | + {PORTA_3, TIMER14, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_0)}, /* TIMER14_CH1 */ |
| 147 | + {PORTA_4, TIMER13, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_4)}, /* TIMER13_CH0 */ |
| 148 | + {PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_1)}, /* TIMER2_CH0 */ |
| 149 | + {PORTA_6, TIMER15, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_5)}, /* TIMER15_CH0 */ |
| 150 | + {PORTA_7, TIMER2, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_1)}, /* TIMER2_CH1 */ |
| 151 | + {PORTA_7, TIMER0, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER0_CH0_ON */ |
| 152 | + {PORTA_7, TIMER13, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_4)}, /* TIMER13_CH0 */ |
| 153 | + {PORTA_7, TIMER16, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_5)}, /* TIMER16_CH0 */ |
| 154 | + {PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER0_CH0 */ |
| 155 | + {PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_2)}, /* TIMER0_CH1 */ |
| 156 | + {PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, IND_GPIO_AF_2)}, /* TIMER0_CH2 */ |
| 157 | + {PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, IND_GPIO_AF_2)}, /* TIMER0_CH3 */ |
| 158 | + {PORTB_0, TIMER2, GD_PIN_FUNC_PWM(2, IND_GPIO_AF_1)}, /* TIMER2_CH2 */ |
| 159 | + {PORTB_0, TIMER0, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_2)}, /* TIMER0_CH1_ON */ |
| 160 | + {PORTB_1, TIMER13, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_0)}, /* TIMER13_CH0 */ |
| 161 | + {PORTB_1, TIMER2, GD_PIN_FUNC_PWM(3, IND_GPIO_AF_1)}, /* TIMER2_CH3 */ |
| 162 | + {PORTB_1, TIMER0, GD_PIN_FUNC_PWM(2, IND_GPIO_AF_2)}, /* TIMER0_CH2_ON */ |
| 163 | + {PORTB_4, TIMER2, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_1)}, /* TIMER2_CH0 */ |
| 164 | + {PORTB_5, TIMER2, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_1)}, /* TIMER2_CH1 */ |
| 165 | + {PORTB_6, TIMER15, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER15_CH0_ON */ |
| 166 | + {PORTB_7, TIMER16, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER16_CH0_ON */ |
| 167 | + {PORTB_8, TIMER15, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER15_CH0 */ |
| 168 | + {PORTB_9, TIMER16, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER16_CH0 */ |
| 169 | + {PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_2)}, /* TIMER0_CH0_ON */ |
| 170 | + {PORTB_14, TIMER14, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_1)}, /* TIMER14_CH0 */ |
| 171 | + {PORTB_14, TIMER0, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_2)}, /* TIMER0_CH1_ON */ |
| 172 | + {PORTB_15, TIMER14, GD_PIN_FUNC_PWM(1, IND_GPIO_AF_1)}, /* TIMER14_CH1 */ |
| 173 | + {PORTB_15, TIMER0, GD_PIN_FUNC_PWM(2, IND_GPIO_AF_2)}, /* TIMER0_CH2_ON */ |
| 174 | + {PORTB_15, TIMER14, GD_PIN_FUNC_PWM(0, IND_GPIO_AF_3)}, /* TIMER14_CH0_ON */ |
| 175 | + {NC, NC, 0} |
| 176 | +}; |
| 177 | + |
| 178 | +/* UART_TX PinMap */ |
| 179 | +const PinMap PinMap_UART_TX[] = { |
| 180 | + {PORTA_2, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART1_TX */ |
| 181 | + {PORTA_8, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* USART1_TX */ |
| 182 | + {PORTA_9, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART0_TX */ |
| 183 | + {PORTA_14, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART1_TX */ |
| 184 | + {PORTB_6, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_0)}, /* USART0_TX */ |
| 185 | + {NC, NC, 0} |
| 186 | +}; |
| 187 | + |
| 188 | +/* UART_RX PinMap */ |
| 189 | +const PinMap PinMap_UART_RX[] = { |
| 190 | + {PORTA_3, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART1_RX */ |
| 191 | + {PORTA_10, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART0_RX */ |
| 192 | + {PORTA_15, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_1)}, /* USART1_RX */ |
| 193 | + {PORTB_0, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_4)}, /* USART1_RX */ |
| 194 | + {PORTB_7, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_PULLUP, IND_GPIO_AF_0)}, /* USART0_RX */ |
| 195 | + {NC, NC, 0} |
| 196 | +}; |
| 197 | + |
| 198 | +/* UART_RTS PinMap */ |
| 199 | +const PinMap PinMap_UART_RTS[] = { |
| 200 | + {PORTA_1, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_1)}, /* USART1_RTS */ |
| 201 | + {PORTA_12, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_1)}, /* USART0_RTS */ |
| 202 | + {NC, NC, 0} |
| 203 | +}; |
| 204 | + |
| 205 | +/* UART_CTS PinMap */ |
| 206 | +const PinMap PinMap_UART_CTS[] = { |
| 207 | + {PORTA_0, USART1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_1)}, /* USART1_CTS */ |
| 208 | + {PORTA_11, USART0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_1)}, /* USART0_CTS */ |
| 209 | + {NC, NC, 0} |
| 210 | +}; |
| 211 | + |
| 212 | +/* SPI_MOSI PinMap */ |
| 213 | +const PinMap PinMap_SPI_MOSI[] = { |
| 214 | + {PORTA_7, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_MOSI_I2S0_SD */ |
| 215 | + {PORTA_14, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_6)}, /* SPI1_MOSI */ |
| 216 | + {PORTB_5, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_MOSI_I2S0_SD */ |
| 217 | + {PORTB_15, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI1_MOSI */ |
| 218 | + {NC, NC, 0} |
| 219 | +}; |
| 220 | + |
| 221 | +/* SPI_MISO PinMap */ |
| 222 | +const PinMap PinMap_SPI_MISO[] = { |
| 223 | + {PORTA_6, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_MISO_I2S0_MCK */ |
| 224 | + {PORTA_13, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_6)}, /* SPI1_MISO */ |
| 225 | + {PORTB_4, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_MISO_I2S0_MCK */ |
| 226 | + {PORTB_14, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI1_MISO */ |
| 227 | + {NC, NC, 0} |
| 228 | +}; |
| 229 | + |
| 230 | +/* SPI_SCLK PinMap */ |
| 231 | +const PinMap PinMap_SPI_SCLK[] = { |
| 232 | + {PORTA_5, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_SCK_I2S0_CK */ |
| 233 | + {PORTB_1, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_6)}, /* SPI1_SCK */ |
| 234 | + {PORTB_3, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_SCK_I2S0_CK */ |
| 235 | + {PORTB_10, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_7)}, /* SPI1_SCK */ |
| 236 | + {PORTB_13, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI1_SCK */ |
| 237 | + {NC, NC, 0} |
| 238 | +}; |
| 239 | + |
| 240 | +/* SPI_SSEL PinMap */ |
| 241 | +const PinMap PinMap_SPI_SSEL[] = { |
| 242 | + {PORTA_4, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_NSS_I2S0_WS */ |
| 243 | + {PORTA_4, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_6)}, /* SPI1_NSS */ |
| 244 | + {PORTA_15, SPI0, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI0_NSS_I2S0_WS */ |
| 245 | + {PORTA_15, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_6)}, /* SPI1_NSS */ |
| 246 | + {PORTB_9, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_7)}, /* SPI1_NSS */ |
| 247 | + {PORTB_12, SPI1, GD_PIN_FUNCTION4(PIN_MODE_AF, GPIO_OTYPE_PP, PIN_PUPD_NONE, IND_GPIO_AF_0)}, /* SPI1_NSS */ |
| 248 | + {NC, NC, 0} |
| 249 | +}; |
| 250 | + |
| 251 | +/* CAN_RD PinMap */ |
| 252 | +const PinMap PinMap_CAN_RD[] = { |
| 253 | + {NC, NC, 0} |
| 254 | +}; |
| 255 | + |
| 256 | +/* CAN_TD PinMap */ |
| 257 | +const PinMap PinMap_CAN_TD[] = { |
| 258 | + {NC, NC, 0} |
| 259 | +}; |
| 260 | + |
0 commit comments