fix(pipeline): send flw/fsw through the LSU in parallel-FU mode

In FunctionalUnits mode, flw and fsw went to the FPU unit because their
class is FloatingPoint. Results from that unit go straight to WB, so the
load never read memory and the store never wrote it. Any value that went
through memory into or out of the float registers was lost; rv32uf
passed 4 of 11 in this mode.

Dispatch them to the LSU and count them as memory operations for the
ordering check. rv32uf now passes 11/11 in all four pipeline modes.
The other modes do not use these paths, and their cycle counts on the
riscv-tests ELFs are unchanged.

Author: Gaok1

crates/raven-engine/src/architectures/riscv32/falcon/pipeline/sim.rs

@@ -2854,8 +2854,19 @@ fn apply_just_committed_visibility_to_mem(slot: &mut PipeSlot, committed: &PipeS
     }
 }
 
+/// `flw` and `fsw` are FloatingPoint by class but access memory: they must go
+/// through the LSU and MEM, not straight from the FPU to WB.
+fn is_float_memory_slot(slot: &PipeSlot) -> bool {
+    matches!(
+        slot.instr
+            .or_else(|| crate::falcon::decoder::decode(slot.word).ok()),
+        Some(Instruction::Flw { .. } | Instruction::Fsw { .. })
+    )
+}
+
 fn parallel_fu_kind_for_slot(slot: &PipeSlot) -> Option<FuKind> {
     match slot.class {
+        InstrClass::FloatingPoint if is_float_memory_slot(slot) => Some(FuKind::Lsu),
         InstrClass::Alu | InstrClass::Multiply | InstrClass::Divide | InstrClass::FloatingPoint => {
             FuKind::from_class(slot.class)
         }
@@ -2885,7 +2896,9 @@ fn parallel_fu_occupancy(state: &PipelineSimState, kind: FuKind) -> usize {
 }
 
 fn is_memory_slot(slot: &PipeSlot) -> bool {
-    !slot.is_bubble && matches!(slot.class, InstrClass::Load | InstrClass::Store)
+    !slot.is_bubble
+        && (matches!(slot.class, InstrClass::Load | InstrClass::Store)
+            || is_float_memory_slot(slot))
 }
 
 fn lsu_dispatch_blocked_by_older_memory(state: &PipelineSimState) -> bool {

tests/support/ui_pipeline_sim.rs

@@ -1667,6 +1667,61 @@ fn f0_result_is_forwarded_like_any_float_register() {
     assert_eq!(cpu_pipe.read(10), 0x12345678);
 }
 
+#[test]
+fn parallel_fu_mode_sends_float_loads_and_stores_through_mem() {
+    // flw/fsw are FloatingPoint by class; they used to go from the FPU
+    // straight to WB, so the load read nothing and the store wrote nothing.
+    let asm = r#"
+.data
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0
+.word 0
+.word 0
+.word 0
+.text
+    la   a1, tdat
+    flw  f1, 4(a1)
+    fsw  f1, 20(a1)
+    lw   a0, 20(a1)
+    flw  f2, 0(a1)
+    fadd.s f3, f1, f2
+    fmv.x.w a2, f3
+    halt
+"#;
+    let (_, cpu_seq, _) = run_sequential(asm);
+    let mut cpu = Cpu::default();
+    let mut mem = CacheController::new(
+        CacheConfig::default(),
+        CacheConfig::default(),
+        vec![],
+        0x4000,
+    );
+    let mut console = Console::default();
+    let cpi = CpiConfig::default();
+    let mut state = PipelineSimState::new();
+    state.mode = crate::falcon::pipeline::PipelineMode::FunctionalUnits;
+    mem.bypass = true;
+    load_program_into_mem(asm, &mut cpu, &mut mem);
+    state.reset_stages(0);
+    for _ in 0..1024 {
+        pipeline_tick(&mut state, &mut cpu, &mut mem, &cpi, &mut console);
+        if state.halted || state.faulted {
+            break;
+        }
+    }
+    // 2.0 stored and reloaded; 2.0 + (-1.0) = 1.0.
+    assert_eq!(
+        [cpu_seq.read(10), cpu_seq.read(12)],
+        [0x4000_0000, 0x3F80_0000]
+    );
+    assert_eq!(
+        [cpu.read(10), cpu.read(12)],
+        [cpu_seq.read(10), cpu_seq.read(12)]
+    );
+}
+
 #[test]
 fn branch_after_two_loads_matches_sequential_behavior() {
     let asm = r#"