Connect design decisions to implementation and verification (#10)

Add concise design decisions, code entry points, evidence limits and
contribution provenance; align repository positioning with the current
Selected Work portfolio. No manual-versus-AI or team contribution
percentage is inferred.

Validation: local source links, repository/architecture validators where
provided, and git diff --check. Runtime implementation is unchanged.

Author: KIM3310

README.md

@@ -143,3 +143,5 @@ The simulator omits prefill, queueing, allocator dynamics within a page, kernel
 ## License
 
 MIT
+
+[Design decisions and implementation evidence](docs/IMPLEMENTATION_NOTES.md)

docs/IMPLEMENTATION_NOTES.md

@@ -0,0 +1,22 @@
+# MemoryFlow Lab: design and evidence
+
+Updated 2026-09-07.
+
+## Design decision
+
+The simulator separates workload demand, page placement and device assumptions. Sensitivity analysis makes capacity and transfer assumptions visible instead of presenting one headline latency as universal.
+
+## Inspect the code
+
+- [src/memoryflow/simulator.py](../src/memoryflow/simulator.py): Model placement and latency trade-offs.
+- [tests/test_simulator.py](../tests/test_simulator.py): Capacity and workload regression cases.
+
+## Scope of the evidence
+
+HBM/CXL figures are analytical estimates. Existing MPS copy/attention measurements have narrower scope and must not be relabeled as real CXL hardware results.
+
+## Contribution and provenance
+
+These notes describe what can be inspected in the repository. Commit history and pull-request diffs preserve the change trail; they do not independently establish manual versus AI-assisted authorship, team roles or contribution percentages. No such percentages are inferred here.
+
+[Project overview](../README.md)

docs/repository-positioning.md

@@ -0,0 +1,11 @@
+# MemoryFlow Lab in Selected Work
+
+Updated 2026-09-07.
+
+The simulator separates workload demand, page placement and device assumptions. Sensitivity analysis makes capacity and transfer assumptions visible instead of presenting one headline latency as universal.
+
+HBM/CXL figures are analytical estimates. Existing MPS copy/attention measurements have narrower scope and must not be relabeled as real CXL hardware results.
+
+This project is selected for its distinct implementation, without implying a particular employment role or startup category.
+
+[Source entry points and attribution](IMPLEMENTATION_NOTES.md)