A comprehensive evaluation and hardware implementation of a Double Pulse Test (DPT) platform for Silicon Carbide (SiC) MOSFETs. This project features a novel Vertical Multi-Loop PCB Layout designed to proactively cancel magnetic flux, significantly reducing parasitic inductance and switching losses in high-frequency wide-bandgap (WBG) applications.
- Overview
- Key Specifications & Improvements
- System Architecture
- Progressive Design Methodology
- Verification & Experimental Results
- Tools Used
As power electronics transition towards high-frequency and high-density systems, SiC MOSFETs offer superior performance over traditional Silicon devices. However, high switching speeds exacerbate the impact of circuit parasitic parameters, leading to severe voltage overshoot, current ringing, and increased switching losses.
This project tackles this challenge from both a theoretical and hardware-level perspective:
- Simulation & Modeling: Built an LTspice DPT model to quantitatively evaluate the impact of parasitic resistance, inductance, and capacitance on SiC MOSFET dynamics.
- PCB Layout Innovation: Proposed and designed a Vertical Multi-Loop PCB layout utilizing adjacent layer magnetic flux cancellation principles.
- Hardware Validation: Constructed a full hardware DPT platform (incorporating a TMS320F28377D DSP and a UCC21530 isolated driver) to validate the theoretical and simulated improvements against a traditional single-loop layout.
The performance of the proposed Vertical Multi-Loop Layout was rigorously tested against a standard Vertical Single-Loop Layout using the Infineon IMZ120R090M1H (1200V SiC MOSFET).
| Parameter | Single-Loop Layout | Vertical Multi-Loop Layout | Improvement |
|---|---|---|---|
| Power Loop Parasitic Inductance (L_loop) | 34.52 nH | 25.01 nH | - 27.5% |
| Gate Loop Parasitic Inductance (L_gs) | 14.49 nH | 9.47 nH | - 34.6% |
| Turn-on Time (t_on) | 80.6 ns | 55.6 ns | - 31.0% |
| Turn-off Time (t_off) | 229.2 ns | 173.2 ns | - 24.4% |
| Turn-on Energy Loss (E_on) | 243.4 µJ | 211.1 µJ | - 13.3% |
| Turn-off Energy Loss (E_off) | 156.6 µJ | 140.0 µJ | - 10.6% |
| Current Overshoot (I_d) | 32.27% | 11.42% | - 20.85% |
The Double Pulse Test (DPT) platform is integrated into a single, highly compact PCB containing the DSP controller, isolated gate driver, and the SiC half-bridge power stage.
- Control Generation: The TI TMS320F28377D DSP generates precisely timed dual-pulse PWM signals via its ePWM modules.
- Signal Translation & Isolation: A level-shifter scales the 3.3V signals to 5V, feeding the TI UCC21530 isolated dual-channel gate driver. The driver provides reinforced isolation (5.7 kVrms) and strong sink/source capabilities to quickly charge/discharge the SiC MOSFET's junction capacitances.
- Power Stage Operation: The lower SiC MOSFET acts as the Device Under Test (DUT), switching an 800V DC bus across a 250 µH inductive load. The upper SiC MOSFET's intrinsic body diode acts as the freewheeling path.
-
Data Acquisition: A high-bandwidth coaxial shunt (CSD01A, 0.01 ohm, 400 MHz) precisely captures the nanosecond-scale drain current transients (
$I_d$ ) alongside high-voltage differential probes for$V_{ds}$ and$V_{gs}$ .
Before layout implementation, an equivalent DPT circuit was established in LTspice to isolate and analyze the effects of specific parasitic parameters.
-
Gate Loop: Discovered that increasing
$L_{gs}$ induces severe$V_{gs}$ ringing, while$R_g$ and$C_{gs}$ act as damping factors that slow down switching speeds but suppress oscillations. -
Power Loop: Revealed that the stray bus inductance (
$L_{loop}$ ) is the primary contributor to severe$V_{ds}$ overshoots during turn-off ($dV/dt$ ), directly threatening device reliability.
To physically mitigate the parasitic inductance, I engineered a Vertical Multi-Loop PCB Layout based on the right-hand rule of magnetic flux.
Design Methodology:
- Interlayer Current Inversion: Conductors with opposite current directions (e.g., DC bus forward and return paths) were placed on adjacent PCB layers (Top and Inner 1) to maximize magnetic field self-cancellation.
- Multi-Loop Expansion: Instead of a simple single loop, the power and gate paths were distributed across a 4-layer stack-up. Same-direction currents were spaced further apart to weaken mutual coupling, while opposite-direction paths were tightly coupled vertically.
-
Kelvin Source Utilization: Leveraging the TO-247-4 package, the gate drive return path was completely decoupled from the high-dI/dt power loop, effectively nullifying common-source inductance (
$L_{ss}$ ) interference.
ANSYS Q3D Extractor was utilized to extract the RLCG matrices, verifying a 65% reduction in theoretical parallel conductor inductance when employing the 4-layer multi-loop structure.
The physical prototype was realized on a 4-layer PCB designed in Altium Designer.
- Power Devices: Infineon IMZ120R090M1H (1200V, 26A) SiC MOSFETs (TO-247-4).
- Firmware: A custom interrupt-driven C program was deployed on the DSP via Code Composer Studio (CCS) to ensure real-time, jitter-free duty cycle modifications for the double-pulse sequence.
-
Data Processing: Developed an automated MATLAB script to reliably identify
$t_{on}$ and$t_{off}$ boundaries, integrate power waveforms for$E_{on}$ /$E_{off}$, and calculate overshoots, overcoming the limitations of manual oscilloscope interpretation amidst high-frequency noise.
The experimental validation matched the theoretical and simulation predictions flawlessly. Under rated conditions (
-
Switching Speed & Loss: The optimized layout reduced the turn-on time by 31.0% and the turn-off time by 24.4%. This faster switching directly translated to a 13.3% reduction in turn-on energy loss (
$E_{on}$ ) and a 10.6% reduction in turn-off energy loss ($E_{off}$ ). - Signal Integrity: Parasitic ringing was substantially mitigated. The voltage overshoot was suppressed by ~5%, and the current overshoot was slashed by nearly 21%, ensuring robust and safe operation of the SiC MOSFET.
| Tool | Application in Project |
|---|---|
| Altium Designer | Hardware schematic entry and 4-layer PCB layout routing |
| LTspice | DPT circuit simulation and parasitic parameter sweep analysis |
| ANSYS Q3D Extractor | 3D electromagnetic field analysis and parasitic RLCG extraction |
| Code Composer Studio (CCS) | DSP firmware development in C for precise ePWM control |
| MATLAB | Custom algorithm development for automated switching transient analysis and data post-processing |
Gate Driver Circuit Design for Wide Band Gap Power Devices · Nanyang Technological University (NTU)