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Add flipflop timing diagram #4750

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Merged
BsAtHome merged 2 commits into from
Nov 1, 2026
Merged

Add flipflop timing diagram #4750

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dd2d452
docs: add timing diagram for flipflop component
hansu Oct 30, 2026
cbac7b5
flipflop: initialize out-not to 1
hansu Oct 30, 2026
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23 changes: 21 additions & 2 deletions src/hal/components/flipflop.comp
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Original file line number Diff line number Diff line change
@@ -1,10 +1,29 @@
component flipflop "D type flip-flop";

description
"""
....
┌─────┐ ┌─────┐ ┌─────
clk: ─────┘ └─────┘ └─────┘
────────┐ ┌xxxxxxxxxxxxx
data: └────────────┘xxxxxxxxxxxxx
┌─────────────
set: ─────────────────────┘
─────────────────┐ ┌────┐
reset: └─────────┘ └──
┌───────────┐ ┌─────┐ ┌──
out: ─────┘ └───┘ └────┘
─────┐ ┌───┐ ┌────┐
out-not: └───────────┘ └─────┘ └──
....
""";

pin in bool data_ "data input";
pin in bool clk "clock, rising edge writes data to out";
pin in bool set "when true, force out true";
pin in bool reset "when true, force out false; overrides set";
pin io bool out "output";
pin io bool out-not "inverted output";
pin io bool out = 0 "output";
pin io bool out-not = 1 "inverted output";
option data flipflop_data;

option period no;
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