The objective of this project was to design and simulate a complete transimpedance amplifier (TIA) in the AMS C35B4 0.35 µm CMOS technology, covering the full analog IC design workflow within the Cadence Virtuoso environment.
The scope of work included:
- selecting a suitable circuit architecture (low-voltage cascode) optimized for a 3.3 V supply, wideband operation, and low-power constraints
- deriving all input design parameters based on the project specification
- performing device-level design calculations, including transconductance estimation, bias current selection, and transistor geometry optimization
- implementing the amplifier schematic together with a complete biasing subsystem
- preparing a comprehensive simulation environment (testbench) for DC, AC, noise, PSRR, and frequency-response analyses
- executing a full PVT analysis across all process corners (TT/SS/FF/SF/FS), three temperatures (−40°C, 27°C, 125°C), and supply-voltage variations (VDD ±10%)
- evaluating the stability and dynamic behavior of the amplifier under nominal and extreme operating conditions
- comparing all simulation results with the initial design targets and identifying worst-case operating scenarios
| Parameter | Value |
|---|---|
| Architecture | Low-voltage cascode |
| GDC | 45 dB |
| fu | 150 MHz |
| Cin | 300 fF |
| CL | 4 pF |
| IDD | minimal |
A transimpedance amplifier (TIA) is a front-end circuit that converts an input current into a corresponding output voltage, typically operating with very small signal levels, high source impedance, and a significant amount of input capacitance. The bandwidth of such an amplifier is directly influenced by the transconductance of the input transistor: higher transconductance allows the circuit to achieve a wider bandwidth for a given input capacitance. This necessitates selecting devices that operate reliably in saturation, with a well-controlled overdrive voltage and minimal bias current, in order to meet the bandwidth and gain requirements while keeping power consumption low.
Designing the TIA in the AMS C35B4 process with a 3.3 V supply requires careful management of the available voltage headroom, since the transistors must remain in saturation even at low supply voltages while still providing sufficiently high output resistance. For this reason, a low-voltage cascode architecture was selected. This topology enhances output resistance, enables the amplifier to reach the target gain of approximately 45 dB with minimal current consumption, and significantly reduces the impact of channel-length modulation on overall performance.
The design workflow involved determining the required transconductance based on the target 150 MHz bandwidth and the 300 fF input capacitance, followed by selecting the bias current and device geometries using Id–Vgs characteristics. After defining the operating points, DC simulations were carried out to confirm saturation of all devices and the stability of the biasing network. A dedicated testbench was prepared for AC and noise analyses, including a closed feedback loop, a 4 pF output load, and a complete biasing infrastructure. The frequency-domain simulations provided the actual unity-gain bandwidth, stability margin, gain roll-off characteristics, and the influence of input capacitance on pole placement. Noise analysis identified the dominant contributors, principally the current noise of the input device and the resistive noise from the biasing network.
Due to the limitations of the 0.35 µm technology and the low operating currents, a comprehensive PVT analysis was performed. This included five process corners (TT, SS, FF, SF, FS), three temperatures (−40°C, 27°C, 125°C), and a supply-voltage tolerance of ±10%. The simulations showed that the slow process corner at elevated temperature and reduced supply voltage yields the most pronounced degradation—manifested as reduced transconductance, lower bandwidth, and diminished stability margin due to decreased bias currents and increased channel resistance. Conversely, in the fast corner at low temperature, transconductance increases, which improves bandwidth but can reduce the phase margin and make the amplifier more susceptible to oscillation under capacitive loading. These observations align with the expected behavior of MOS transistors under extreme operating conditions and confirm that the low-voltage cascode topology, when properly dimensioned, maintains full functionality across the entire PVT space. The amplifier meets the design requirements under nominal conditions and retains an adequate stability margin even in the majority of worst-case scenarios.
The design process began by determining the required transconductance of the input transistor based on the target bandwidth of 150 MHz and the input capacitance of 300 fF. Achieving such a bandwidth necessitates that the input device provide sufficiently high incremental gain while operating with a minimal bias current, which in turn constrains the allowable overdrive voltage and the attainable transconductance. Based on these requirements, the bias current of the input stage was selected to simultaneously meet the bandwidth specification and minimize power consumption. At such low current levels, maintaining a high output resistance becomes critical, which further supports the decision to employ a cascode architecture.
After determining the required transconductance, the next step involved selecting the geometry of the input and cascode transistors. The relationship between transconductance, drain current, and device dimensions was analyzed using Id–Vgs characteristics generated in Cadence. The minimum channel length that ensures stable saturation at low bias currents was established first, followed by selecting the channel width to achieve the target transconductance at the chosen overdrive voltage. The remaining transistors—including those forming the cascode stages and the current mirrors—were dimensioned to provide sufficient gain, maintain proper biasing conditions, and minimize current variation across process and temperature changes.
Once the dimensions of all transistors had been determined, DC simulations were performed to verify the operating points. These simulations confirmed that every device remained in saturation, that the bias currents were stable, and that the cascode structure preserved the required voltage differentials to achieve high output resistance. A dedicated testbench was then prepared for frequency-domain analysis, incorporating a 4 pF load and a closed feedback loop representative of the TIA’s actual operating conditions. The AC analysis enabled evaluation of the achievable bandwidth, gain roll-off characteristics, and stability margin. The results confirmed that the selected operating points and device geometries meet the intended design specifications.
In the next stage, the channel width of the input transistor was determined. The analysis focused on evaluating how the drain current, transconductance, and overdrive voltage vary with transistor width, assuming a previously selected minimum channel length that ensures stable saturation at low bias currents. Using Id–Vgs characteristics generated in Cadence, the minimum width required to achieve the target transconductance at the chosen bias current was identified. Further increases in width were assessed in terms of their impact on dynamic performance and the resulting input capacitance, ensuring an appropriate balance between bandwidth, stability, and power consumption. The results enabled an unambiguous selection of the transistor width that meets all design requirements.
The designed transimpedance amplifier employs a low-voltage cascode architecture, chosen to increase the output resistance and stabilize the amplifier’s operating parameters under a limited 3.3 V supply. This topology is well suited for achieving high gain at very low bias currents, as it minimizes the impact of channel-length modulation and ensures that all transistors operate reliably in saturation. Cascoding the input and output devices maintains nearly constant drain–source voltages at critical nodes, enabling the circuit to achieve high output resistance and stable biasing conditions regardless of load variations.
The amplifier structure consists of an input transistor that performs the primary current-to-voltage conversion, combined with a cascode device that suppresses variations in drain–source voltage and increases effective current gain. On the positive side of the signal path, an analogous PMOS cascode stage is used to stabilize operating points and preserve gain characteristics across process and temperature variations. The biasing network relies on carefully dimensioned current mirrors, which provide a stable reference current and maintain appropriate overdrive voltages to keep all transistors in saturation.
The entire architecture was designed with consideration for the constraints imposed by the large input capacitance and the 4 pF output load. The high output resistance achieved through the cascode structure enables the amplifier to maintain the required gain, while the carefully selected operating points ensure stable pole placement, resulting in an adequate phase margin and reliable closed-loop operation. The device arrangement and biasing strategy minimize sensitivity to process, temperature, and supply variations, which was confirmed through PVT analysis.
This architecture represents a balanced compromise between low power consumption, high output resistance, and stable operation under a limited supply voltage, making it well suited for high-sensitivity, wide-bandwidth applications implemented in 0.35 µm CMOS technology.
The prepared transimpedance amplifier incorporates a complete biasing network designed to establish all required operating points, ensuring correct saturation, target gain performance, and stable operation across the intended process variations.
The simulations were carried out in the Cadence environment and included DC, AC, noise, and closed-loop stability analyses. The initial step involved verifying the operating points, confirming that all transistors remained in saturation and that the biasing network provided stable current levels regardless of loading conditions. The DC analysis demonstrated balanced current distribution within the cascode branches and correct operation of the current mirrors, both of which are essential for achieving high output resistance and maintaining the intended gain.
The AC analysis enabled characterization of the amplifier’s actual frequency response. The achieved bandwidth met the design specifications, and the gain profile exhibited behavior typical of cascode architectures, with a dominant pole setting the initial roll-off and additional poles introduced by the output load and device capacitances. A sufficient phase margin was preserved, ensuring stable closed-loop operation of the TIA, even with the 4 pF load. These results validate the chosen operating points and transistor geometries.
Noise simulations showed that the input transistor is the dominant source of noise, consistent with expectations for low-current TIAs with high input impedance. The noise level increases with frequency, while the noise contributions from the biasing network and cascode devices remain secondary. The resulting noise spectrum confirms that the amplifier is suitable for high-sensitivity, wide-band applications while maintaining low power consumption.
The power-supply rejection (PSRR) analysis further evaluated the circuit’s resilience to supply variations. The PSRR characteristic exhibits a gradual decline with increasing frequency, yet the attenuation within the amplifier’s operating band remains sufficient to prevent supply fluctuations from adversely affecting the output. These results align with the behavior typically observed in low-voltage cascode structures, where limited headroom and low bias currents inherently influence rejection performance.
oinp:
v_outn; ac deg(V):
gain:
gain_db:
phase_ac:
input noise:
PSRR:
Using the test environment:
The completed project confirms that the low-voltage cascode architecture is well suited for a transimpedance amplifier implemented in 0.35 µm CMOS technology, particularly under a limited supply voltage and low bias current conditions. This topology enabled the achievement of high output resistance, stable operating points, and gain consistent with the design requirements, despite the stringent power constraints. The frequency-domain results demonstrated compliance with the target bandwidth, while the obtained phase margin was sufficient to ensure stable closed-loop operation.
The noise analysis verified that the input transistor is the dominant noise contributor, which is expected for low-current TIAs with high input impedance. Nevertheless, the overall noise level remained within acceptable limits for high-sensitivity applications. The evaluation of power-supply rejection showed that the circuit provides adequate immunity to supply disturbances within the relevant frequency range, and its PSRR profile is consistent with the behavior of cascode-based amplifiers.
The PVT analysis indicated that the most critical operating conditions arise in the slow process corner at elevated temperature and reduced supply voltage, where reductions in transconductance, bandwidth, and stability were observed. Despite these challenges, the amplifier maintained full functionality across the entire set of process, temperature, and voltage variations, reflecting a robust biasing strategy and appropriately sized transistors.
In summary, the designed transimpedance amplifier meets the intended specifications for gain, bandwidth, stability, and noise under nominal conditions and continues to operate correctly under worst-case scenarios. The results validate the adopted design assumptions and demonstrate the effectiveness of the chosen architecture for implementing a low-current analog front-end in the AMS C35B4 technology.