fix(perf): unset NCCL_NET_PLUGIN and tune B200 DSv3 256GPU recipe for NCCLEP rc5

- Remove NCCL_NET_PLUGIN from env to avoid plugin interference with NCCL EP
- Set moe_use_grouped_tensor=False for 256GPU B200 fp8mx config
- Add graph_capture_record_stream_reuse:True to PYTORCH_CUDA_ALLOC_CONF
- Remove NCCL_EP_HT_EM_PULL_PUSH env var

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

Author: bhargaveede

scripts/performance/bootstrap.py

@@ -52,6 +52,7 @@ def _apply_recipe_environment(recipe) -> None:
         if not isinstance(value, (str, int, float, bool)):
             raise TypeError(f"Environment variable {name!r} must have a scalar value, got {type(value).__name__}.")
         os.environ.setdefault(name, str(value))
+    os.environ.pop("NCCL_NET_PLUGIN", None)
 
 
 def uses_ncclep(recipe) -> bool:

src/megatron/bridge/perf_recipes/deepseek/b200/deepseek_v3.py

@@ -152,20 +152,19 @@ def deepseek_v3_pretrain_256gpu_b200_fp8mx_config() -> ConfigContainer:
     cfg.comm_overlap.overlap_moe_expert_parallel_comm = True
     # Device-side expert token counts: the legacy grouped MLP path syncs tokens_per_expert to the
     # host every layer, which serializes the CPU behind the GPU when dispatch is fast.
-    cfg.model.moe_use_grouped_tensor = True
+    cfg.model.moe_use_grouped_tensor = False
     # Keep process settings next to the recipe so users can see the exact benchmark environment.
     cfg.env_vars = {
         **COMMON_PERF_ENV_VARS,
         # CUDA stream scheduling for this model and parallel layout.
         "CUDA_DEVICE_MAX_CONNECTIONS": 32,
         # CUDA graph and allocator behavior for this recipe.
         "NCCL_GRAPH_REGISTER": 0,
-        "PYTORCH_CUDA_ALLOC_CONF": "expandable_segments:True",
+        "PYTORCH_CUDA_ALLOC_CONF": "expandable_segments:True,graph_capture_record_stream_reuse:True",
         "TORCH_NCCL_AVOID_RECORD_STREAMS": 1,
         # NCCL user-buffer and launch settings.
         "NCCL_NVLS_ENABLE": 0,
         # NCCL EP dispatcher mode and one GPU per rank.
-        "NCCL_EP_HT_EM_PULL_PUSH": 1,
         # Transformer Engine overlap settings for this model.
         "NVTE_BWD_LAYERNORM_SM_MARGIN": 20,
         "NVTE_FWD_LAYERNORM_SM_MARGIN": 20,