@@ -59,6 +59,9 @@ def nemotron_3_nano_pretrain_8gpu_vr200_bf16_config() -> ConfigContainer:
5959def nemotron_3_nano_pretrain_8gpu_vr200_fp8mx_config () -> ConfigContainer :
6060 """Nemotron 3 Nano pretrain: 8× VR200, FP8-MX (alias of GB300)."""
6161 cfg = _build_nemotron_3_nano_gb300_mxfp8 ()
62+ cfg .model .use_transformer_engine_op_fuser = True
63+ cfg .model .moe_mlp_glu_interleave_size = 32
64+ cfg .mixed_precision .fp8_dot_product_attention = True
6265 # Keep process settings next to the recipe so users can see the exact benchmark environment.
6366 cfg .env_vars = {
6467 ** COMMON_PERF_ENV_VARS ,
@@ -76,7 +79,9 @@ def nemotron_3_nano_pretrain_8gpu_vr200_fp8mx_config() -> ConfigContainer:
7679 "NVLINK_DOMAIN_SIZE" : 72 ,
7780 "USE_MNNVL" : 1 ,
7881 # Transformer Engine overlap settings for this model.
82+ "CUDNNFE_CLUSTER_OVERLAP_MARGIN" : 8 ,
7983 "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
84+ "NVTE_CUTEDSL_FUSED_GROUPED_MLP" : 1 ,
8085 "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
8186 # Use cuDNN LayerNorm for this measured baseline.
8287 "NVTE_NORM_BWD_USE_CUDNN" : 1 ,
@@ -145,6 +150,9 @@ def nemotron_3_super_pretrain_64gpu_vr200_bf16_config() -> ConfigContainer:
145150def nemotron_3_super_pretrain_64gpu_vr200_fp8mx_config () -> ConfigContainer :
146151 """Nemotron 3 Super pretrain: 64× VR200, FP8-MX (alias of GB300)."""
147152 cfg = _build_nemotron_3_super_gb300_mxfp8 ()
153+ cfg .model .use_transformer_engine_op_fuser = True
154+ cfg .model .moe_mlp_glu_interleave_size = 32
155+ cfg .mixed_precision .fp8_dot_product_attention = True
148156 # Keep process settings next to the recipe so users can see the exact benchmark environment.
149157 cfg .env_vars = {
150158 ** COMMON_PERF_ENV_VARS ,
@@ -162,7 +170,9 @@ def nemotron_3_super_pretrain_64gpu_vr200_fp8mx_config() -> ConfigContainer:
162170 "NVLINK_DOMAIN_SIZE" : 72 ,
163171 "USE_MNNVL" : 1 ,
164172 # Transformer Engine overlap settings for this model.
173+ "CUDNNFE_CLUSTER_OVERLAP_MARGIN" : 8 ,
165174 "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
175+ "NVTE_CUTEDSL_FUSED_GROUPED_MLP" : 1 ,
166176 "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
167177 }
168178 return cfg
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