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[None][chore] Mass merge release/1.3 branch back to main (batch 2) - #20843
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SimengLiu-nv wants to merge 23 commits into
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SimengLiu-nv wants to merge 23 commits into
SimengLiu-nv wants to merge 23 commits into
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SimengLiu-nv
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Barry-Delaney,
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longlee0622,
lori-ren,
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yunruis
October 22, 2026 23:12
….3: Pin GB300 GLM-5 ctx workers to their GPU's NUMA node in perf-sanity Forward-port of release/1.3 PR NVIDIA#20136 (release/1.3 commit 47c0479) to main. The release PR cherry-picked main PR NVIDIA#20103, which was closed without merging, so this change was not on main. Signed-off-by: chenfeiz0326 <203214996+chenfeiz0326@users.noreply.github.com> Co-authored-by: chenfeiz0326 <203214996+chenfeiz0326@users.noreply.github.com> Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Process-wide workspace caches keyed by `Mapping` with a per-mapping lock… Forward-port of release/1.3 PR NVIDIA#19847 (release/1.3 commit 84461c6) to main. Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Mike Iovine <miovine@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Keep session-prefetch output off sys.stdout Forward-port of release/1.3 PR NVIDIA#20152 (release/1.3 commit ca9c5b6) to main. Signed-off-by: qgai <qgai@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Fix spelling and capitalization in release/1.3 docs Forward-port of release/1.3 PR NVIDIA#20193 (release/1.3 commit f92ba89) to main. Signed-off-by: Stanley Sun <stsun@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Use coherent managed memory for EPLB when GDRCopy is unavailable Forward-port of release/1.3 PR NVIDIA#20156 (release/1.3 commit 248825e) to main. Signed-off-by: qgai <qgai@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Run the launcher test's python3 stand-in with -S so start-up hooks cannot… Forward-port of release/1.3 PR NVIDIA#20195 (release/1.3 commit cd4cc17) to main. Adapted to main: main never had the release-only waives for nvbugs/6911393, so only the launcher test change is ported. Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
…1.3: Share TRTLLM-Gen FMHA cubins across isolated MPI ranks Forward-port of release/1.3 PR NVIDIA#20264 (release/1.3 commit 74173d4) to main. The release PR cherry-picked main PR NVIDIA#20257, which was closed without merging, so this change was not on main. Signed-off-by: chenfeiz0326 <203214996+chenfeiz0326@users.noreply.github.com> Co-authored-by: chenfeiz0326 <203214996+chenfeiz0326@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Detect dead MPI pool manager thread in MpiPoolSession Forward-port of release/1.3 PR NVIDIA#20248 (release/1.3 commit 9ec0b50) to main. Signed-off-by: Asfiya Baig <asfiyab@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Bound FP8 MLA page-table loads for partial tiles Forward-port of release/1.3 PR NVIDIA#20415 (release/1.3 commit c98395b) to main. Adapted to main: the fix is applied to tensorrt_llm/_torch/attention/kernels/blackwell/mla/mla_decode_fp8.py, where NVIDIA#19275 moved the CuTe DSL MLA decode kernels, and the new test passes the FP8 softmax/output scales as device tensors at inputs[10:12], the runner input contract main adopted in NVIDIA#19960. Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
…TS refresh backport review tests and docs Forward-port of release/1.3 PR NVIDIA#20381 (release/1.3 commit 4317a84) to main. Adapted to main: main keeps PrimTS block-sparse plan caches on the attention metadata (TrtllmAttentionMetadata.fmha_plan_caches) and documents SageAttention for the contiguous block-sparse path. The summary-contract paragraph goes right after the routing-payload paragraph in ATTENTION_DEVELOPER_GUIDE.md, ahead of both. With the module-level cpu_only marker removed, the per-test cpu_only marker also goes on main's test_block_sparse_plan_cache_lives_on_the_metadata and on the three CPU-only SageAttention tests from main's NVIDIA#20224, so they keep running on the CPU stage. Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Scope NCCL window leases in helix attention tests Forward-port of release/1.3 PR NVIDIA#20588 (release/1.3 commit 356b1a2) to main. Adapted to main: main never had the release-only waives for nvbugs/6932241 and 6932265, so only the helix test changes are ported. Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Reject conflicting LoRA adapter identities Forward-port of release/1.3 PR NVIDIA#20344 (release/1.3 commit d747876) to main. Adapted to main: NVIDIA#20043 made BaseWorker._load_lora_adapter return None and load with _lora_model_config only, so the identity checks wrap main's call and the new tests check load calls and bindings instead of a return value. Main's test_lora_ownership.py (NVIDIA#20605) builds BaseWorker without __init__, so its _make_runtime also sets the adapter identity map and locks. Signed-off-by: Yibin Li <109242046+yibinl-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Validate native transfer destinations before submission Forward-port of release/1.3 PR NVIDIA#20346 (release/1.3 commit 2331e1f) to main. Adapted to main: main-only disaggregated tests that drive Sender._submit_transfer (test_retirement_deadline.py, test_kv_transfer_fail_stop.py, test_transfer_late_settlement.py) now pass a WRITE request whose remote descriptors pass the new pre-submission check. Signed-off-by: Yibin Li <109242046+yibinl-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Mount a 640G /dev/shm for online-EPLB perf cases Forward-port of release/1.3 PR NVIDIA#20531 (release/1.3 commit 2401956) to main. Adapted to main: the new tests reuse the submit-module fixtures and the _fake_sinfo helper that main already defines in test_perf_submit.py. Signed-off-by: xxi <xxi@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Fix rank-asymmetric NCCL window allocation hang during PARALLEL autotuning Forward-port of release/1.3 PR NVIDIA#20657 (release/1.3 commit 0c88e43) to main. Signed-off-by: Lori Ren <lorir@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Keep Nemotron-H SSM cache dtype unset Forward-port of release/1.3 PR NVIDIA#20284 (release/1.3 commit 0312481) to main. Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
….3: Restrict coordinator HTTP cluster storage to loopback Forward-port of release/1.3 PR NVIDIA#20651 (release/1.3 commit 135d95a) to main. Signed-off-by: Yibin Li <109242046+yibinl-nvidia@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
…1.3: Use FlashInfer for Gemma4 NVFP4 perf on SM107 Forward-port of release/1.3 PR NVIDIA#20794 (release/1.3 commit 025f9ae) to main. Also updates the comment on main's SM121 Gemma 4 override (NVIDIA#20210) to mention the new SM107 override. Signed-off-by: Ruodi Lu <ruodil@users.noreply.github.com> Co-authored-by: Ruodi Lu <ruodil@users.noreply.github.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
…etry deployment IDs as UUIDs Forward-port of release/1.3 PR NVIDIA#20777 (release/1.3 commit 6c172f3) to main. Adapted to main: the new payload test patches _HEARTBEAT_STOP, which main renamed from _REPORTER_STOP. Signed-off-by: Maxim Gluhovskoi <mgluhovskoi@nvidia.com> Signed-off-by: Simeng Liu <simengl@nvidia.com>
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Dev Engineer Review
This forward-port combines fixes across attention, checkpoint loading, disaggregation, distributed execution, EPLB, telemetry, and documentation. It adds APIs and code paths, changes defaults and dispatch behavior, and updates test infrastructure.
Verify FMHA head-size-104 dispatch and kernel generation across supported architectures. Check that NCCL window-allocation suppression is restored after parallel autotuning, and that shared cubin reads and publication handle concurrent ranks. Verify NIXL descriptor validation and transfer ownership, LoRA adapter identity rules, Qwen3.5 INT4 packing, and Mistral image-processing behavior.
No current review findings or severity counts were supplied. The reported
tests/unittest/scripts/test_perf_submit.pyrun passed 127 tests, but the supplied CI summary also reports a failed/LLM/main/L0_MergeRequest_PRpipeline. GPU tests were not run locally. Overall completion status is not established.QA Engineer Review
The change set adds and updates tests for FMHA head size 104, Pixtral and sparse attention, MLA page tables, checkpoint mapping, distributed workspace caching, cubin pooling, NIXL transfers, LoRA identity, and EPLB mounts. It also updates CI and QA test lists, moves one Qwen3 case between QA lists, and removes one waiver.
The head-104 C++ test is listed in
test-db/l0_b200.yml,test-db/l0_gb202.yml, andtest-db/l0_rtx_pro_6000.yml. The Pixtral test is listed in the GB202 and RTX Pro 6000 lists. The cubin-pool test is listed intest-db/l0_cpu.yml. The Qwen3 case moves fromqa/llm_function_core.txttoqa/llm_function_multinode.txt. The supplied list changes do not identify entries for the other new tests.Coverage verdict: needs follow-up. The supplied evidence does not establish that every new test is included in an appropriate CI or manual-QA list. GPU tests were not run locally, and the reported merge-request pipeline failed.
Per-File QA Perspective
Source and documentation files
cpp/kernels/fmha_v2/setup.py— Verify generated head-size-104 mask kernels across SM90, SM100, and SM120, including dtype, warp-specialization, and tiling conditions.cpp/tensorrt_llm/common/ncclUtils.cpp— Verify suppressed allocations return an invalid buffer before communicator and size validation.cpp/tensorrt_llm/common/ncclUtils.h— Verify the setter declaration matches its implementation and thread-local contract.cpp/tensorrt_llm/executor/cache_transmission/nixl_utils/transferAgent.cpp— Verify descriptor splitting against recorded VMM regions, including behavior when an agent has no recorded map.cpp/tensorrt_llm/kernels/fmhaDispatcher.cpp— Verify head-size-104 dispatch selects FMHA v2 only for the specified SM100-family types and masks.cpp/tensorrt_llm/runtime/moeLoadBalancer/hostAccessibleDeviceAllocator.cpp— Verify managed-memory support, allocation advice, and fallback behavior across GDRCopy and direct-host-access configurations.cpp/tensorrt_llm/runtime/moeLoadBalancer/hostAccessibleDeviceAllocator.h— Verify the new access-mode state and documented preference order match allocator behavior.cpp/tensorrt_llm/thop/allreduceOp.cpp— Verify the new operator returns the prior suppression state and behaves as intended without multi-device support.tensorrt_llm/_torch/attention/kernels/blackwell/mla/mla_decode_fp8.py— Verify partial page-table tiles do not read beyond the table.tensorrt_llm/_torch/autotuner.py— Verify suppression applies only to distributed parallel tuning and is restored after profiling errors.tensorrt_llm/_torch/configs/nemotron_h.py— Verify theNonecache-dtype default resolves through the intended model-dtype logic.tensorrt_llm/_torch/disaggregation/native/transfer.py— Verify WRITE preflight failures prevent submission and retire ownership correctly; verify bounced sends validate original destinations.tensorrt_llm/_torch/disaggregation/nixl/_agent_py.py— VerifyMemoryDescsconversion and errors match native-agent expectations.tensorrt_llm/_torch/distributed/ops.py— Verify process-wide workspace reuse is safe across threads and distinct mappings.tensorrt_llm/_torch/flashinfer_cubin_pool.py— Verify pool eligibility, checksum validation, atomic publication, and fallback behavior.tensorrt_llm/_torch/flashinfer_utils.py— Verify pool installation runs only when FlashInfer is available and preserves normal loader behavior.tensorrt_llm/_torch/models/checkpoints/hf/qwen3_5_weight_mapper.py— Verify packed-INT4 dimensions, scales, biases, and AWQ preprocessing for split and fused layouts.tensorrt_llm/_torch/models/checkpoints/hf/qwen4_exp_weight_mapper.py— Verify shared TP-rank concatenation preserves projection ordering.tensorrt_llm/_torch/models/modeling_minimaxm3.py— Verify reshaped GQA SDPA output preserves batch, KV-head, and group ordering.tensorrt_llm/_torch/models/modeling_mistral.py— Verify image geometry and scheduling metadata for both processors, including text-only checkpoint behavior.tensorrt_llm/_torch/models/modeling_utils.py— Verify TP-rank concatenation preserves rank-major ordering and rejects invalid shapes.tensorrt_llm/_torch/modules/linear.py— Verify optional AWQ pre-quant scales are loaded, sharded, and cleared correctly.tensorrt_llm/_torch/nccl_window_graph.py— Verify the context manager restores the previous suppression state, including after exceptions.tensorrt_llm/bench/tuning/heuristics.py— Verify missing andautocache dtypes use the model dtype when sizing Mamba cache memory.tensorrt_llm/executor/base_worker.py— Verify LoRA ID bindings reject conflicting identities while allowing aliases and retries after unsuccessful lookups.tensorrt_llm/llmapi/mpi_session.py— Verifycheck_worker_error()reports a dead manager thread but not a live or stopped pool.tensorrt_llm/serve/disagg_coordinator.py— Verify HTTP cluster-storage scope validation rejects unsafe host and scope combinations.tensorrt_llm/usage/usage_lib.py— Verify deployment IDs are normalized as UUIDs and invalid values are omitted from telemetry.jenkins/scripts/perf/benchmark_utils.py— Verify EPLB detection handles inline and file-based configs and adds the shared-memory mount only when needed.jenkins/scripts/perf/local/submit.py— Verify local submission passes the loaded config into mount generation without changing other launch arguments.jenkins/scripts/perf/submit.py— Verify CI submission changes container mounts only and preserves other srun arguments.docs/source/blogs/tech_blog/blog13_Inference_Time_Compute_Implementation_in_TensorRT-LLM.md— Documentation-only model-name capitalization change.docs/source/developer-guide/sparse-attention-development-guide.md— Verify the documented summary contract matches kernel weighting for partial KV blocks.docs/source/features/sparse-attention.md— Verify the public sparse-attention contract states means, valid-token counts, and no pre-weighting.docs/source/llm-api/index.md— Verify shared-cubin documentation matches implementation and environment-variable behavior.docs/source/overview.md— Documentation-only capitalization correction.docs/source/release-notes.md— Documentation-only typo correction.examples/wide_ep/README.md— Verify the managed-memory fallback is limited to the stated coherent platforms.tensorrt_llm/_torch/attention/ATTENTION_DEVELOPER_GUIDE.md— Verify developer guidance matches sparse-kernel proxy weighting.tensorrt_llm/usage/schemas/README.md— Verify UUID normalization guidance matches telemetry behavior.Test-code files
cpp/tests/unit_tests/executor/transferAgentTest.cpp— Covers NIXL descriptor subranges, unknown agents, writes, and adjacent VMM chunks; no test-list entry is identified in the supplied summaries.cpp/tests/unit_tests/kernels/fmhaHead104Test.cpp— Covers packed-QKV head-size-104 output across masks, dtypes, and ragged lengths; its integration test is listed in GPU test lists.cpp/tests/unit_tests/runtime/hostAccessibleDeviceAllocatorTest.cu— Covers direct host access to managed memory without GDRCopy; no test-list entry is identified in the supplied summaries.tests/integration/defs/cpp/conftest.py— Adds the build fixture for the head-104 C++ test; the integration test is listed in GPU test lists.tests/integration/defs/cpp/test_unit_tests.py— Adds the head-104 integration test for targets 100 and 120; corresponding entries appear in the supplied GPU test-list changes.tests/unittest/_torch/attention/multi_gpu/test_mha_helix.py— Covers attention output lifetime inside an NCCL window tensor scope; no test-list entry is identified.tests/unittest/_torch/attention/multi_gpu/test_mla_helix.py— Covers MLA output lifetime inside an NCCL window tensor scope; no test-list entry is identified.tests/unittest/_torch/attention/sparse/test_prims_ts_block_sparse.py— Covers partial-block proxy weighting and CPU/GPU behavior; no test-list entry is identified.tests/unittest/_torch/attention/test_cute_dsl_mla_page_table.py— Covers unpadded page-table widths and partial final pages on SM100/SM103; no test-list entry is identified.tests/unittest/_torch/attention/test_fmha_v2_head_size_coverage.py— Covers generated head-size-104 kernel inclusion and exclusions; no test-list entry is identified.tests/unittest/_torch/attention/test_pixtral_head104_attention.py— Covers Pixtral head-size-104 attention on supported architectures; listed for GB202 and RTX Pro 6000.tests/unittest/_torch/attention/test_prims_ts_attention_backend.py— Covers lazy rescaling around the skip threshold, including CUDA graph replay; no test-list entry is identified.tests/unittest/_torch/attention/test_prims_ts_fmha.py— Updates wrapper mocks to use autospec across FMHA paths; no test-list entry is identified.tests/unittest/_torch/distributed/test_allreduce_workspace_cache.py— Covers cross-thread reuse, concurrent initialization, and distinct mappings; no test-list entry is identified.tests/unittest/_torch/flashinfer/test_flashinfer_cubin_pool.py— Covers pool eligibility, reuse, corruption, failed downloads, concurrency, and installation; listed intest-db/l0_cpu.yml.tests/unittest/_torch/modeling/test_modeling_mistral.py— Covers image geometry and scheduling for both Mistral processors and text-only checkpoints; no test-list entry is identified.tests/unittest/_torch/modeling/test_qwen4_exp_support.py— Tests the shared TP-rank concatenation helper; no test-list entry is identified.tests/unittest/_torch/models/checkpoints/hf/test_qwen3_5_weight_mapper.py— Covers INT4 mapping, layouts, TP sizes, scales, and invalid inputs; no test-list entry is identified.tests/unittest/_torch/models/test_minimax_m3.py— Covers dense SDPA decode against explicit GQA repetition with scattered cache pages; no test-list entry is identified.tests/unittest/_torch/models/test_qwen3_5_int4_loading.py— Covers INT4 mapping into GDN projections across TP ranks and optional scales; listed intest-db/l0_b200.yml.tests/unittest/_torch/modules/test_linear_uneven_tp.py— Covers optional AWQ pre-quant scales in COLUMN and ROW modes; listed intest-db/l0_b200.yml.tests/unittest/_torch/multi_gpu/test_allocate_output_buffer_kinds.py— Covers NCCL window allocation after distributed parallel tuning; no test-list entry is identified.tests/unittest/_torch/test_custom_config_registration.py— Covers Nemotron-H cache dtype resolution for absent and explicit values; no test-list entry is identified.tests/unittest/disaggregated/test_agent.py— Covers Python NIXL descriptor conversion, metadata results, and errors; no test-list entry is identified.tests/unittest/disaggregated/test_coordinator_worker.py— Covers loopback-only HTTP cluster-storage validation; no test-list entry is identified.tests/unittest/disaggregated/test_kv_transfer_fail_stop.py— Updates WRITE request fixtures for descriptor validation; no test-list entry is identified.tests/unittest/disaggregated/test_retirement_deadline.py— Updates NIXL WRITE fixtures across retirement and deadline cases; no test-list entry is identified.tests/unittest/disaggregated/test_transfer_late_settlement.py— Updates sender fixtures for descriptor checks; no test-list entry is identified.tests/unittest/disaggregated/test_transfer_ownership_regressions.py— Covers preflight rejection, submission failure, retirement state, and sender ownership; no test-list entry is identified.tests/unittest/executor/test_base_worker.py— Covers LoRA identity conflicts, aliases, retry behavior, and concurrency; no test-list entry is identified.tests/unittest/executor/test_proxy_fast_death.py— Covers dead MPI manager-thread detection; no test-list entry is identified.tests/unittest/llmapi/test_mpi_launcher_shutdown.py— Covers launcher startup without site initialization; no test-list entry is identified.tests/unittest/others/test_bench.py— Covers Nemotron cache sizing for unset,auto, and float32 dtypes; no test-list entry is identified.tests/unittest/scripts/test_perf_submit.py— Covers EPLB detection and CI/local mount generation; the PR objectives report 127 tests passed.tests/unittest/usage/test_reporter.py— Covers UUID normalization and invalid deployment IDs across telemetry events; no test-list entry is identified.tests/test_common/session_prefetcher.py— Changes diagnostic output handling; verify messages remain available through file descriptor 1.tests/unittest/_torch/peft/test_lora_ownership.py— Updates runtime setup with LoRA identity and locking fields; no test-list entry is identified.Test-list and test configuration files
tests/integration/test_lists/qa/llm_function_core.txt— Removes the Qwen3 NVFP4 test entry; the case moves to the multinode QA list.tests/integration/test_lists/qa/llm_function_multinode.txt— Adds the Qwen3 NVFP4 test entry.tests/integration/test_lists/test-db/l0_b200.yml— Adds the head-104 C++ test and Qwen3.5 INT4/AWQ tests to pre-merge coverage.tests/integration/test_lists/test-db/l0_cpu.yml— Adds the FlashInfer cubin-pool unit test.tests/integration/test_lists/test-db/l0_gb202.yml— Adds head-104 and Pixtral attention tests.tests/integration/test_lists/test-db/l0_rtx_pro_6000.yml— Adds head-104 and Pixtral attention tests.tests/integration/test_lists/waives.txt— Removes the waiver forTestMistralLarge3_675B::test_nvfp4_4gpus[latency_moe_trtllm]; verify the test is suitable to run without the waiver.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_1k1k_con1_ctx1_dep2_gen1_tep4_mtp3_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_1k1k_con4096_ctx1_dep2_gen1_dep8_eplb256_mtp1_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_1k1k_con512_ctx1_dep2_gen1_dep32_eplb0_mtp3_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_8k1k_con1024_ctx1_dep2_gen1_dep8_eplb256_mtp1_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_8k1k_con1_ctx1_dep2_gen1_tep8_eplb0_mtp3_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.tests/scripts/perf-sanity/disaggregated/gb300_glm-5-fp4_8k1k_con512_ctx1_dep2_gen1_dep32_eplb0_mtp3_ccb-NIXL.yaml— Adds NUMA-aware worker affinity for the context worker; verify the launcher accepts the setting.Description
Second mass merge of release/1.3 fixes that are still missing from main, following #20232. It forward-ports the 23 release/1.3 PRs that, as of 2026-10-22, have no counterpart on main and no open PR to main. Each original PR is one commit, and each commit message links back to the original release PR and commit and keeps the original author and sign-off. Commits that needed changes for main carry an "Adapted to main" note in their message. The branch was rebased onto main
79d1d922dcon 2026-10-26.MultimodalItemMetadatacontract (#20391)Mappingwith a per-mapping lock…_load_lora_adapter() -> None(#20043); updates main'stest_lora_ownership.pyfixture (#20605)_HEARTBEAT_STOP(renamed on main)Notes:
test_attention_mla) is kept; it can be removed once the [https://nvbugs/6862662][fix] Bound FP8 MLA page-table loads for partial tiles #20415 fix is confirmed on B200.RemoteTaskgainssys_path, the… #20058, [TRTLLMINF-474][infra] Upgrade NGC PyTorch base image to 26.09 (#19679) #20146, [https://nvbugs/6784181][fix] Fix test_relative_path_validity: generated-doc allowlist and skip installed envs (cherry-pick #19405, #19403) #20601, [None][fix] Cherry-pick #20203, #20581, #20575 to release/1.3 #20689) and those already covered by open PRs to main.Test Coverage
test_qwen3_5_int4_loading.py,test_fmha_v2_head_size_coverage.py,test_pixtral_head104_attention.py,fmhaHead104Test.cpp,test_allreduce_workspace_cache.py,test_flashinfer_cubin_pool.py,test_cute_dsl_mla_page_table.py, the LoRA identity tests intest_base_worker.py, the EPLB/dev/shmtests intest_perf_submit.py, and the coordinator, telemetry and MPI pool tests.test_cute_dsl_mla_page_table.py(FP8 scale inputs),test_base_worker.py(no return value),test_retirement_deadline.py,test_kv_transfer_fail_stop.pyandtest_transfer_late_settlement.py(WRITE requests for the new pre-submission check),test_prims_ts_block_sparse.py(cpu_only markers, including on main's Sage tests),test_modeling_mistral.py(main'sget_mm_item_metadataAPI and tuple fields), and main'stest_lora_ownership.py(adapter identity state in its worker fixture).tests/unittest/scripts/test_perf_submit.pypassed (127 tests). GPU tests were not run locally and rely on CI.PR Checklist
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