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[PyTorch] Fix NVFP4 metadata in compiled Linear operations - #3628

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pggPL merged 16 commits into
NVIDIA:mainfrom
pggPL:fix_nvfp4_compile_nd
Oct 20, 2026
Merged

pggPL merged 16 commits into
NVIDIA:mainfrom
pggPL:fix_nvfp4_compile_nd

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@pggPL pggPL commented Oct 5, 2026 •

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Fix NVFP4 torch.compile failures for non-matrix Linear inputs and incorrect gradients from Linear operations with bias. Native Bias backward can produce compact scales while its fake output describes GEMM-swizzled scales, causing compiled GEMM to interpret the reconstructed tensor incorrectly.

Native execution and fake metadata now share alignment requirements through NVFP4Quantizer. C++ reads the RHT-fusion environment flag only when needed; Python reads it explicitly so Dynamo can guard changes. TensorSpec preserves the actual scale layout, and NVFP4 metadata matches native packed columnwise buffers and row-scaled amax shapes. Columnwise-only shape warnings are skipped during tracing.

Bias backward uses a small shared fake helper. Follow-up normalization and activation operations should use the same fused-output metadata helper.

Regression coverage stays in test_torch_compile.py, including dynamic shapes, environment changes, quantizer configurations and CUDA Graphs. Focused checks on SM89 passed: 98 tests passed and 44 skipped, including hardware-dependent NVFP4 cases. The C++ extension build and binding checks, pre-commit and changed-source pylint also passed. Validation of the final NVFP4 test matrix on SM100 remains pending; PyTorch L0 CI is requested separately.

Fixes #3626.

Describe columnwise FP4 buffers with the flattened 2D shape used by native quantization. Cover 3D and 4D inputs, singleton dimensions, RHT variants, buffer metadata, and compiled forward/backward with CUDA graphs.

Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
pggPL added 2 commits October 12, 2026 16:04
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Preserve the actual scale layout across custom-op boundaries and describe Bias backward output with the native fused-quantization layout. Keep the columnwise storage warning outside tracing. Cover compiled ops.Linear gradients with compact and swizzled scales, including disabled RHT fusion and CUDA Graphs.

Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
@pggPL pggPL changed the title Fix NVFP4 compile metadata for non-matrix inputs [PyTorch] Fix NVFP4 metadata in compiled Linear operations Oct 12, 2026
pggPL added 2 commits October 12, 2026 16:58
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Exercise current and block FP8, MXFP8, and NVFP4 variants in the existing fresh-process test. Keep scale-layout defaults in create_metadata instead of duplicating them in TensorSpec initialization.

Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
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greptile-apps Bot commented Oct 12, 2026 •

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RetriggerView in GreptileConfidence Score: 5/5

[Medium impact] The changes appear safe to merge; no actionable new defects were found.

Summary

This PR aligns compiled NVFP4 metadata with native outputs for Linear operations with bias and non-matrix inputs.

  • Compiled NVFP4 outputs describe the scale layout native code produces.
  • NVFP4 fake tensors use the packed shapes and amax sizes native code uses.

The latest changes flatten the columnwise shape helper and test a size-one middle dimension. No new actionable issues were found. Tests were not run during this review.

Diagram

%%{init: {'theme': 'neutral'}}%%
flowchart LR
  A[NVFP4 quantizer settings] --> B[Shared alignment rules]
  B --> C[Native output scale layout]
  B --> D[Fake output scale layout]
  D --> E[TensorSpec metadata]
  C --> F[Compiled GEMM]
  E --> F
Loading

Reviews (12) · Last reviewed commit: "Fix NVFP4 columnwise shapes in the share..." · Reviewed by Greptile

pggPL added 8 commits October 12, 2026 18:54
Skip TE autocast for unquantized inputs and give the eager reference its own model so quantizer usage changes do not invalidate compiled graphs.

Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Expose native alignment requirements through a metadata-only binding. Keep symbolic shape checks and environment reads visible to Dynamo, and cover dynamic batches and configuration changes through the Bias custom op.

Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
@pggPL

pggPL commented Oct 14, 2026

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/te-ci pytorch L0

pggPL added 3 commits October 14, 2026 13:06
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
Signed-off-by: Pawel Gadzinski <pgadzinski@nvidia.com>
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pggPL commented Oct 19, 2026

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/te-ci pytorch

@pggPL
pggPL merged commit f0b1096 into NVIDIA:main Oct 20, 2026
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[bug] NVFP4 + torch.compile: errors with 3D input

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