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conf/evalsoc: fix pmu event mappings to match corrected nmsis_bench.h
Align the riscv,pmu node event-to-mhpmevent and raw-event-to-mhpmcounters mappings with the corrected performance monitor event definitions in NMSIS nmsis_bench.h (see nuclei-sdk commit da74dcb): - Move ICACHE_PREFETCH_MISS from incorrect Type 3 idx 9 (sel=3, 0x93) to correct Type 1 idx 6 (sel=1, 0x61) per ISA manual errata. - Fix scrambled raw event comments for Event Types 2/3 and add the missing Type 0 idx 0 (Dcache read) / Type 3 idx 25 (BTB write miss) raw event entries so the table matches the actual event encoding. - Add VPU commit events (Type 2, idx 4-7): total/load/store/ computational instruction commit counts (0x42/0x52/0x62/0x72). Signed-off-by: Huaqi Fang <578567190@qq.com>
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Lines changed: 910 additions & 92 deletions

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‎conf/evalsoc/nuclei_rv32imac.dts‎

Lines changed: 252 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,258 @@
215215
clock-frequency = <25000000>;
216216
};
217217

218+
pmu {
219+
compatible = "riscv,pmu";
220+
/* https://perf.wiki.kernel.org/index.php/Tutorial#Events */
221+
/* eg. perf stat -B coremark */
222+
/* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */
223+
/* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */
224+
/* Note: in the dts comment, v2 means your Nuclei RISC-V CPU need to support HPM_VER = Version 2 */
225+
riscv,event-to-mhpmevent =
226+
/* Type #0 SBI_PMU_HW_CPU_CYCLES -> Nuclei event sel=0 idx=1 Cycle count */
227+
<0x00001 0x00000000 0x00000010>,
228+
/* Type #0 SBI_PMU_HW_INSTRUCTIONS -> Nuclei event sel=0 idx=2 Retired instruction count */
229+
<0x00002 0x00000000 0x00000020>,
230+
/* Type #0 SBI_PMU_HW_CACHE_REFERENCES -> v2, Nuclei event sel=1 idx=8 L2-Cache access count */
231+
<0x00003 0x00000000 0x00000081>,
232+
/* Type #0 SBI_PMU_HW_CACHE_MISSES -> v2, Nuclei event sel=1 idx=9 L2-Cache miss count */
233+
<0x00004 0x00000000 0x00000091>,
234+
/* Type #0 SBI_PMU_HW_BRANCH_INSTRUCTIONS -> v2, Nuclei event sel=2 idx=2 Branch instruction commit count */
235+
<0x00005 0x00000000 0x00000022>,
236+
/* Type #0 SBI_PMU_HW_BRANCH_MISSES -> v2, Nuclei event sel=2 idx=3 Branch predict fail count */
237+
<0x00006 0x00000000 0x00000032>,
238+
/* Type #0 SBI_PMU_HW_BUS_CYCLES -> v2, Nuclei event sel=1 idx=10 Memory bus request count */
239+
<0x00007 0x00000000 0x000000A1>,
240+
/* Type #0 SBI_PMU_HW_STALLED_CYCLES_FRONTEND -> v2, Nuclei event sel=1 idx=11 IFU stall cycle count */
241+
<0x00008 0x00000000 0x000000B1>,
242+
/* Type #0 SBI_PMU_HW_STALLED_CYCLES_BACKEND -> v2, Nuclei event sel=1 idx=12 EXU stall cycle count */
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<0x00009 0x00000000 0x000000C1>,
244+
/* Type #0 SBI_PMU_HW_REF_CPU_CYCLES -> v2, Nuclei event sel=1 idx=13 Timer count */
245+
<0x0000A 0x00000000 0x000000D1>,
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/* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=0 Dcache read count */
247+
<0x10000 0x00000000 0x00000003>,
248+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=1 Dcache read miss count */
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<0x10001 0x00000000 0x00000013>,
250+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=2 Dcache write count */
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<0x10002 0x00000000 0x00000023>,
252+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=3 Dcache write miss count */
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<0x10003 0x00000000 0x00000033>,
254+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=4 Dcache prefetch count */
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<0x10004 0x00000000 0x00000043>,
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/* Type #1 SBI_PMU_HW_CACHE_L1D(0) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=5 Dcache prefetch miss count */
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<0x10005 0x00000000 0x00000053>,
258+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=6 Icache read count */
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<0x10008 0x00000000 0x00000063>,
260+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) MISS(1) -> v1, Nuclei event sel=1 idx=1 Icache read miss count */
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<0x10009 0x00000000 0x00000011>,
262+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
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<0x1000C 0x00000000 0x00000083>,
264+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=1 idx=6 Icache prefetch miss count */
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<0x1000D 0x00000000 0x00000061>,
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/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
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<0x10010 0x00000000 0x000000A3>,
268+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
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<0x10011 0x00000000 0x000000B3>,
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/* Type #1 SBI_PMU_HW_CACHE_LL(2) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=12 L2 Cache write count */
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<0x10012 0x00000000 0x000000C3>,
272+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=13 L2 Cache write miss count */
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<0x10013 0x00000000 0x000000D3>,
274+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=14 L2 Cache prefetch count */
275+
<0x10014 0x00000000 0x000000E3>,
276+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=15 L2 Cache prefetch miss count */
277+
<0x10015 0x00000000 0x000000F3>,
278+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=16 DTLB read count */
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<0x10018 0x00000000 0x00000103>,
280+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=17 DTLB read miss count */
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<0x10019 0x00000000 0x00000113>,
282+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=18 DTLB write count */
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<0x1001A 0x00000000 0x00000123>,
284+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=19 DTLB write miss count */
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<0x1001B 0x00000000 0x00000133>,
286+
/* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=20 ITLB read count */
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<0x10020 0x00000000 0x00000143>,
288+
/* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) MISS(1) -> v1, Nuclei event sel=1 idx=3 ITLB read miss count */
289+
<0x10021 0x00000000 0x00000031>,
290+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=22 BTB read count */
291+
<0x10028 0x00000000 0x00000163>,
292+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=23 BTB read miss count */
293+
<0x10029 0x00000000 0x00000173>,
294+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=24 BTB write count */
295+
<0x1002A 0x00000000 0x00000183>,
296+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=25 BTB write miss count */
297+
<0x1002B 0x00000000 0x00000193>,
298+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
299+
<0x10030 0x00000000 0x000000A3>,
300+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
301+
<0x10031 0x00000000 0x000000B3>,
302+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=12 L2 Cache write count */
303+
<0x10032 0x00000000 0x000000C3>,
304+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=13 L2 Cache write miss count */
305+
<0x10033 0x00000000 0x000000D3>,
306+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=14 L2 Cache prefetch count */
307+
<0x10034 0x00000000 0x000000E3>,
308+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=15 L2 Cache prefetch miss count */
309+
<0x10035 0x00000000 0x000000F3>;
310+
/* make hpm3-6 counter available for all hardware events */
311+
riscv,event-to-mhpmcounters =
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<0x00001 0x0000000A 0x00000078>,
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<0x10000 0x00010035 0x00000078>;
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/* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */
315+
riscv,raw-event-to-mhpmcounters =
316+
/* Event Types 0 events - 0x1 Cycle count */
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<0x00000000 0x00000010 0xffffffff 0xffffffff 0x00000078>,
318+
/* Event Types 0 events - 0x2 Retired instruction count */
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<0x00000000 0x00000020 0xffffffff 0xffffffff 0x00000078>,
320+
/* Event Types 0 events - 0x3 Integer load instruction (includes LR) */
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<0x00000000 0x00000030 0xffffffff 0xffffffff 0x00000078>,
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/* Event Types 0 events - 0x4 Integer store instruction (includes SC) */
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<0x00000000 0x00000040 0xffffffff 0xffffffff 0x00000078>,
324+
/* Event Types 0 events - 0x5 Atomic memory operation (do not include LR and SC) */
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<0x00000000 0x00000050 0xffffffff 0xffffffff 0x00000078>,
326+
/* Event Types 0 events - 0x6 System instruction */
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<0x00000000 0x00000060 0xffffffff 0xffffffff 0x00000078>,
328+
/* Event Types 0 events - 0x7 Integer computational instruction(excluding multiplication/division/remainder) */
329+
<0x00000000 0x00000070 0xffffffff 0xffffffff 0x00000078>,
330+
/* Event Types 0 events - 0x8 Conditional branch */
331+
<0x00000000 0x00000080 0xffffffff 0xffffffff 0x00000078>,
332+
/* Event Types 0 events - 0x9 Taken conditional branch */
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<0x00000000 0x00000090 0xffffffff 0xffffffff 0x00000078>,
334+
/* Event Types 0 events - 0xa JAL instruction */
335+
<0x00000000 0x000000a0 0xffffffff 0xffffffff 0x00000078>,
336+
/* Event Types 0 events - 0xb JALR instruction */
337+
<0x00000000 0x000000b0 0xffffffff 0xffffffff 0x00000078>,
338+
/* Event Types 0 events - 0xc Return instruction */
339+
<0x00000000 0x000000c0 0xffffffff 0xffffffff 0x00000078>,
340+
/* Event Types 0 events - 0xd Control transfer instruction (CBR+JAL+JALR) */
341+
<0x00000000 0x000000d0 0xffffffff 0xffffffff 0x00000078>,
342+
/* Event Types 0 events - 0xe fence instruction(Not include fence.i) */
343+
<0x00000000 0x000000e0 0xffffffff 0xffffffff 0x00000078>,
344+
/* Event Types 0 events - 0xf Integer multiplication instruction */
345+
<0x00000000 0x000000f0 0xffffffff 0xffffffff 0x00000078>,
346+
/* Event Types 0 events - 0x10 Integer division/remainder instruction */
347+
<0x00000000 0x00000100 0xffffffff 0xffffffff 0x00000078>,
348+
/* Event Types 0 events - 0x11 Floating-point load instruction */
349+
<0x00000000 0x00000110 0xffffffff 0xffffffff 0x00000078>,
350+
/* Event Types 0 events - 0x12 Floating-point store instruction */
351+
<0x00000000 0x00000120 0xffffffff 0xffffffff 0x00000078>,
352+
/* Event Types 0 events - 0x13 Floating-point addition/subtraction */
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<0x00000000 0x00000130 0xffffffff 0xffffffff 0x00000078>,
354+
/* Event Types 0 events - 0x14 Floating-point multiplication */
355+
<0x00000000 0x00000140 0xffffffff 0xffffffff 0x00000078>,
356+
/* Event Types 0 events - 0x15 Floating-point fused multiply-add (FMADD, FMSUB,FNMSUB, FNMADD) */
357+
<0x00000000 0x00000150 0xffffffff 0xffffffff 0x00000078>,
358+
/* Event Types 0 events - 0x16 Floating-point division or square-root */
359+
<0x00000000 0x00000160 0xffffffff 0xffffffff 0x00000078>,
360+
/* Event Types 0 events - 0x17 Other floating-point instruction */
361+
<0x00000000 0x00000170 0xffffffff 0xffffffff 0x00000078>,
362+
/* Event Types 0 events - 0x18 Conditional branch(BXX) prediction fail */
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<0x00000000 0x00000180 0xffffffff 0xffffffff 0x00000078>,
364+
/* Event Types 0 events - 0x19 JALR prediction fail */
365+
<0x00000000 0x00000190 0xffffffff 0xffffffff 0x00000078>,
366+
/* Event Types 0 events - 0x1a POP prediction fail */
367+
<0x00000000 0x000001a0 0xffffffff 0xffffffff 0x00000078>,
368+
/* Event Types 0 events - 0x1b FENCEI instruction */
369+
<0x00000000 0x000001b0 0xffffffff 0xffffffff 0x00000078>,
370+
/* Event Types 0 events - 0x1c SFENCE instruction */
371+
<0x00000000 0x000001c0 0xffffffff 0xffffffff 0x00000078>,
372+
/* Event Types 0 events - 0x1d ECALL instruction */
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<0x00000000 0x000001d0 0xffffffff 0xffffffff 0x00000078>,
374+
/* Event Types 0 events - 0x1e EXCEPTION instruction */
375+
<0x00000000 0x000001e0 0xffffffff 0xffffffff 0x00000078>,
376+
/* Event Types 0 events - 0x1f INTERRUPT instruction */
377+
<0x00000000 0x000001f0 0xffffffff 0xffffffff 0x00000078>,
378+
/* Event Types 1 events - 0x1 Icache read miss count */
379+
<0x00000000 0x00000011 0xffffffff 0xffffffff 0x00000078>,
380+
/* Event Types 1 events - 0x2 Dcache read/write miss count */
381+
<0x00000000 0x00000021 0xffffffff 0xffffffff 0x00000078>,
382+
/* Event Types 1 events - 0x3 ITLB read miss count */
383+
<0x00000000 0x00000031 0xffffffff 0xffffffff 0x00000078>,
384+
/* Event Types 1 events - 0x4 DTLB read/write miss count */
385+
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
386+
/* Event Types 1 events - 0x5 Main TLB miss count */
387+
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
388+
/* Event Types 1 events - 0x6 Icache prefetch miss count */
389+
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
390+
/* Event Types 1 events - 0x7 Reserved */
391+
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
392+
/* Event Types 1 events - 0x8 L2-Cache access count */
393+
<0x00000000 0x00000081 0xffffffff 0xffffffff 0x00000078>,
394+
/* Event Types 1 events - 0x9 L2-Cache miss count */
395+
<0x00000000 0x00000091 0xffffffff 0xffffffff 0x00000078>,
396+
/* Event Types 1 events - 0xa Memory bus request count */
397+
<0x00000000 0x000000a1 0xffffffff 0xffffffff 0x00000078>,
398+
/* Event Types 1 events - 0xb IFU stall cycle count */
399+
<0x00000000 0x000000b1 0xffffffff 0xffffffff 0x00000078>,
400+
/* Event Types 1 events - 0xc EXU stall cycle count */
401+
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
402+
/* Event Types 1 events - 0xd Timer count */
403+
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
404+
/* Event Types 2 events - 0x2 Branch instruction commit count */
405+
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
406+
/* Event Types 2 events - 0x3 Branch predict fail count */
407+
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
408+
/* Event Types 2 events - 0x4 VPU total instruction commit count */
409+
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
410+
/* Event Types 2 events - 0x5 VPU load instruction commit count */
411+
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
412+
/* Event Types 2 events - 0x6 VPU store instruction commit count */
413+
<0x00000000 0x00000062 0xffffffff 0xffffffff 0x00000078>,
414+
/* Event Types 2 events - 0x7 VPU computational instruction commit count */
415+
<0x00000000 0x00000072 0xffffffff 0xffffffff 0x00000078>,
416+
/* Event Types 3 events - 0x0 Dcache read count */
417+
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000078>,
418+
/* Event Types 3 events - 0x1 Dcache read miss count */
419+
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
420+
/* Event Types 3 events - 0x2 Dcache write count */
421+
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
422+
/* Event Types 3 events - 0x3 Dcache write miss count */
423+
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
424+
/* Event Types 3 events - 0x4 Dcache prefetch count */
425+
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
426+
/* Event Types 3 events - 0x5 Dcache prefetch miss count */
427+
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
428+
/* Event Types 3 events - 0x6 Icache read count */
429+
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
430+
/* Event Types 3 events - 0x7 Reserved */
431+
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
432+
/* Event Types 3 events - 0x8 Icache prefetch count */
433+
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
434+
/* Event Types 3 events - 0x9 Reserved */
435+
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
436+
/* Event Types 3 events - 0xa L2-Cache read count */
437+
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
438+
/* Event Types 3 events - 0xb L2-Cache read miss count */
439+
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
440+
/* Event Types 3 events - 0xc L2-Cache write count */
441+
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
442+
/* Event Types 3 events - 0xd L2-Cache write miss count */
443+
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
444+
/* Event Types 3 events - 0xe L2-Cache prefetch hit count */
445+
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
446+
/* Event Types 3 events - 0xf L2-Cache prefetch miss count */
447+
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
448+
/* Event Types 3 events - 0x10 DTLB read count */
449+
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
450+
/* Event Types 3 events - 0x11 DTLB read miss count */
451+
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
452+
/* Event Types 3 events - 0x12 DTLB write count */
453+
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
454+
/* Event Types 3 events - 0x13 DTLB write miss count */
455+
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
456+
/* Event Types 3 events - 0x14 ITLB read count */
457+
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
458+
/* Event Types 3 events - 0x15 Reserved */
459+
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
460+
/* Event Types 3 events - 0x16 BTB read count */
461+
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
462+
/* Event Types 3 events - 0x17 BTB read miss count */
463+
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
464+
/* Event Types 3 events - 0x18 BTB write count */
465+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>,
466+
/* Event Types 3 events - 0x19 BTB write miss count */
467+
<0x00000000 0x00000193 0xffffffff 0xffffffff 0x00000078>;
468+
};
469+
218470
plic0: interrupt-controller@1c000000 {
219471
#interrupt-cells = <1>;
220472
compatible = "riscv,plic0";

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