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fanghuaqifanghuaqi
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conf/evalsoc: fix pmu event mappings to match corrected nmsis_bench.h
Align the riscv,pmu node event-to-mhpmevent and raw-event-to-mhpmcounters mappings with the corrected performance monitor event definitions in NMSIS nmsis_bench.h (see nuclei-sdk commit da74dcb): - Move ICACHE_PREFETCH_MISS from incorrect Type 3 idx 9 (sel=3, 0x93) to correct Type 1 idx 6 (sel=1, 0x61) per ISA manual errata. - Fix scrambled raw event comments for Event Types 2/3 and add the missing Type 0 idx 0 (Dcache read) / Type 3 idx 25 (BTB write miss) raw event entries so the table matches the actual event encoding. - Add VPU commit events (Type 2, idx 4-7): total/load/store/ computational instruction commit counts (0x42/0x52/0x62/0x72). Signed-off-by: Huaqi Fang <578567190@qq.com>
1 parent cbd14b9 commit 37c06d9

1 file changed

Lines changed: 40 additions & 34 deletions

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‎conf/evalsoc/nuclei_rv64imafdc.dts‎

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -242,8 +242,8 @@
242242
<0x10009 0x00000000 0x00000011>,
243243
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
244244
<0x1000C 0x00000000 0x00000083>,
245-
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=9 Icache prefetch miss count */
246-
<0x1000D 0x00000000 0x00000093>,
245+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=1 idx=6 Icache prefetch miss count */
246+
<0x1000D 0x00000000 0x00000061>,
247247
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
248248
<0x10010 0x00000000 0x000000A3>,
249249
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
@@ -366,7 +366,7 @@
366366
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
367367
/* Event Types 1 events - 0x5 Main TLB miss count */
368368
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
369-
/* Event Types 1 events - 0x6 Reserved */
369+
/* Event Types 1 events - 0x6 Icache prefetch miss count */
370370
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
371371
/* Event Types 1 events - 0x7 Reserved */
372372
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
@@ -382,64 +382,70 @@
382382
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
383383
/* Event Types 1 events - 0xd Timer count */
384384
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
385-
/* Event Types 2 events - 0x1 VPU store instruction commit count */
386-
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00000078>,
387-
/* Event Types 2 events - 0x2 Reserved */
385+
/* Event Types 2 events - 0x2 Branch instruction commit count */
388386
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
389-
/* Event Types 2 events - 0x3 VPU load instruction commit count */
387+
/* Event Types 2 events - 0x3 Branch predict fail count */
390388
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
391-
/* Event Types 2 events - 0x4 VPU computational instruction commit count */
389+
/* Event Types 2 events - 0x4 VPU total instruction commit count */
392390
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
393-
/* Event Types 2 events - 0x5 Branch predict fail count */
391+
/* Event Types 2 events - 0x5 VPU load instruction commit count */
394392
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
395-
/* Event Types 3 events - 0x1 Icache read count */
393+
/* Event Types 2 events - 0x6 VPU store instruction commit count */
394+
<0x00000000 0x00000062 0xffffffff 0xffffffff 0x00000078>,
395+
/* Event Types 2 events - 0x7 VPU computational instruction commit count */
396+
<0x00000000 0x00000072 0xffffffff 0xffffffff 0x00000078>,
397+
/* Event Types 3 events - 0x0 Dcache read count */
398+
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000078>,
399+
/* Event Types 3 events - 0x1 Dcache read miss count */
396400
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
397-
/* Event Types 3 events - 0x2 L2-Cache read hit count */
401+
/* Event Types 3 events - 0x2 Dcache write count */
398402
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
399-
/* Event Types 3 events - 0x3 DTLB write count */
403+
/* Event Types 3 events - 0x3 Dcache write miss count */
400404
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
401-
/* Event Types 3 events - 0x4 L2-Cache write miss count */
405+
/* Event Types 3 events - 0x4 Dcache prefetch count */
402406
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
403-
/* Event Types 3 events - 0x5 Reserved */
407+
/* Event Types 3 events - 0x5 Dcache prefetch miss count */
404408
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
405-
/* Event Types 3 events - 0x6 Icache prefetch miss count */
409+
/* Event Types 3 events - 0x6 Icache read count */
406410
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
407-
/* Event Types 3 events - 0x7 BTB write count */
411+
/* Event Types 3 events - 0x7 Reserved */
408412
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
409-
/* Event Types 3 events - 0x8 L2-Cache read miss count */
413+
/* Event Types 3 events - 0x8 Icache prefetch count */
410414
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
411-
/* Event Types 3 events - 0x9 DTLB write miss count */
415+
/* Event Types 3 events - 0x9 Reserved */
412416
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
413-
/* Event Types 3 events - 0xa ITLB read count */
417+
/* Event Types 3 events - 0xa L2-Cache read count */
414418
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
415-
/* Event Types 3 events - 0xb BTB read count */
419+
/* Event Types 3 events - 0xb L2-Cache read miss count */
416420
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
417-
/* Event Types 3 events - 0xc Dcache prefetch count */
421+
/* Event Types 3 events - 0xc L2-Cache write count */
418422
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
419-
/* Event Types 3 events - 0xd Icache prefetch count */
423+
/* Event Types 3 events - 0xd L2-Cache write miss count */
420424
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
421-
/* Event Types 3 events - 0xe Dcache write count */
425+
/* Event Types 3 events - 0xe L2-Cache prefetch hit count */
422426
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
423-
/* Event Types 3 events - 0xf DTLB read count */
427+
/* Event Types 3 events - 0xf L2-Cache prefetch miss count */
424428
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
425-
/* Event Types 3 events - 0x10 Dcache write miss count */
429+
/* Event Types 3 events - 0x10 DTLB read count */
426430
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
427-
/* Event Types 3 events - 0x11 BTB write miss count */
431+
/* Event Types 3 events - 0x11 DTLB read miss count */
428432
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
429-
/* Event Types 3 events - 0x12 Dcache read count */
433+
/* Event Types 3 events - 0x12 DTLB write count */
430434
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
431-
/* Event Types 3 events - 0x13 L2-Cache write hit count */
435+
/* Event Types 3 events - 0x13 DTLB write miss count */
432436
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
433-
/* Event Types 3 events - 0x14 L2-Cache prefetch miss count */
437+
/* Event Types 3 events - 0x14 ITLB read count */
434438
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
435-
/* Event Types 3 events - 0x15 BTB read miss count */
439+
/* Event Types 3 events - 0x15 Reserved */
436440
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
437-
/* Event Types 3 events - 0x16 Dcache read miss count */
441+
/* Event Types 3 events - 0x16 BTB read count */
438442
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
439-
/* Event Types 3 events - 0x17 L2-Cache prefetch hit count */
443+
/* Event Types 3 events - 0x17 BTB read miss count */
440444
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
441-
/* Event Types 3 events - 0x18 DTLB read miss count */
442-
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>;
445+
/* Event Types 3 events - 0x18 BTB write count */
446+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>,
447+
/* Event Types 3 events - 0x19 BTB write miss count */
448+
<0x00000000 0x00000193 0xffffffff 0xffffffff 0x00000078>;
443449
};
444450

445451
plic0: interrupt-controller@1c000000 {

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