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fanghuaqifanghuaqi
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conf/evalsoc: fix pmu event mappings to match corrected nmsis_bench.h
Align the riscv,pmu node event-to-mhpmevent and raw-event-to-mhpmcounters mappings with the corrected performance monitor event definitions in NMSIS nmsis_bench.h (see nuclei-sdk commit da74dcb): - Move ICACHE_PREFETCH_MISS from incorrect Type 3 idx 9 (sel=3, 0x93) to correct Type 1 idx 6 (sel=1, 0x61) per ISA manual errata. - Fix scrambled raw event comments for Event Types 2/3 and add the missing Type 0 idx 0 (Dcache read) / Type 3 idx 25 (BTB write miss) raw event entries so the table matches the actual event encoding. - Add VPU commit events (Type 2, idx 4-7): total/load/store/ computational instruction commit counts (0x42/0x52/0x62/0x72). Signed-off-by: Huaqi Fang <578567190@qq.com>
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Lines changed: 40 additions & 34 deletions

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‎conf/evalsoc/nuclei_rv64imafdc.dts‎

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -289,8 +289,8 @@
289289
<0x10009 0x00000000 0x00000011>,
290290
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
291291
<0x1000C 0x00000000 0x00000083>,
292-
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=9 Icache prefetch miss count */
293-
<0x1000D 0x00000000 0x00000093>,
292+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=1 idx=6 Icache prefetch miss count */
293+
<0x1000D 0x00000000 0x00000061>,
294294
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
295295
<0x10010 0x00000000 0x000000A3>,
296296
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
@@ -413,7 +413,7 @@
413413
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
414414
/* Event Types 1 events - 0x5 Main TLB miss count */
415415
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
416-
/* Event Types 1 events - 0x6 Reserved */
416+
/* Event Types 1 events - 0x6 Icache prefetch miss count */
417417
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
418418
/* Event Types 1 events - 0x7 Reserved */
419419
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
@@ -429,64 +429,70 @@
429429
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
430430
/* Event Types 1 events - 0xd Timer count */
431431
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
432-
/* Event Types 2 events - 0x1 VPU store instruction commit count */
433-
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00000078>,
434-
/* Event Types 2 events - 0x2 Reserved */
432+
/* Event Types 2 events - 0x2 Branch instruction commit count */
435433
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
436-
/* Event Types 2 events - 0x3 VPU load instruction commit count */
434+
/* Event Types 2 events - 0x3 Branch predict fail count */
437435
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
438-
/* Event Types 2 events - 0x4 VPU computational instruction commit count */
436+
/* Event Types 2 events - 0x4 VPU total instruction commit count */
439437
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
440-
/* Event Types 2 events - 0x5 Branch predict fail count */
438+
/* Event Types 2 events - 0x5 VPU load instruction commit count */
441439
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
442-
/* Event Types 3 events - 0x1 Icache read count */
440+
/* Event Types 2 events - 0x6 VPU store instruction commit count */
441+
<0x00000000 0x00000062 0xffffffff 0xffffffff 0x00000078>,
442+
/* Event Types 2 events - 0x7 VPU computational instruction commit count */
443+
<0x00000000 0x00000072 0xffffffff 0xffffffff 0x00000078>,
444+
/* Event Types 3 events - 0x0 Dcache read count */
445+
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000078>,
446+
/* Event Types 3 events - 0x1 Dcache read miss count */
443447
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
444-
/* Event Types 3 events - 0x2 L2-Cache read hit count */
448+
/* Event Types 3 events - 0x2 Dcache write count */
445449
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
446-
/* Event Types 3 events - 0x3 DTLB write count */
450+
/* Event Types 3 events - 0x3 Dcache write miss count */
447451
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
448-
/* Event Types 3 events - 0x4 L2-Cache write miss count */
452+
/* Event Types 3 events - 0x4 Dcache prefetch count */
449453
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
450-
/* Event Types 3 events - 0x5 Reserved */
454+
/* Event Types 3 events - 0x5 Dcache prefetch miss count */
451455
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
452-
/* Event Types 3 events - 0x6 Icache prefetch miss count */
456+
/* Event Types 3 events - 0x6 Icache read count */
453457
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
454-
/* Event Types 3 events - 0x7 BTB write count */
458+
/* Event Types 3 events - 0x7 Reserved */
455459
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
456-
/* Event Types 3 events - 0x8 L2-Cache read miss count */
460+
/* Event Types 3 events - 0x8 Icache prefetch count */
457461
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
458-
/* Event Types 3 events - 0x9 DTLB write miss count */
462+
/* Event Types 3 events - 0x9 Reserved */
459463
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
460-
/* Event Types 3 events - 0xa ITLB read count */
464+
/* Event Types 3 events - 0xa L2-Cache read count */
461465
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
462-
/* Event Types 3 events - 0xb BTB read count */
466+
/* Event Types 3 events - 0xb L2-Cache read miss count */
463467
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
464-
/* Event Types 3 events - 0xc Dcache prefetch count */
468+
/* Event Types 3 events - 0xc L2-Cache write count */
465469
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
466-
/* Event Types 3 events - 0xd Icache prefetch count */
470+
/* Event Types 3 events - 0xd L2-Cache write miss count */
467471
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
468-
/* Event Types 3 events - 0xe Dcache write count */
472+
/* Event Types 3 events - 0xe L2-Cache prefetch hit count */
469473
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
470-
/* Event Types 3 events - 0xf DTLB read count */
474+
/* Event Types 3 events - 0xf L2-Cache prefetch miss count */
471475
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
472-
/* Event Types 3 events - 0x10 Dcache write miss count */
476+
/* Event Types 3 events - 0x10 DTLB read count */
473477
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
474-
/* Event Types 3 events - 0x11 BTB write miss count */
478+
/* Event Types 3 events - 0x11 DTLB read miss count */
475479
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
476-
/* Event Types 3 events - 0x12 Dcache read count */
480+
/* Event Types 3 events - 0x12 DTLB write count */
477481
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
478-
/* Event Types 3 events - 0x13 L2-Cache write hit count */
482+
/* Event Types 3 events - 0x13 DTLB write miss count */
479483
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
480-
/* Event Types 3 events - 0x14 L2-Cache prefetch miss count */
484+
/* Event Types 3 events - 0x14 ITLB read count */
481485
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
482-
/* Event Types 3 events - 0x15 BTB read miss count */
486+
/* Event Types 3 events - 0x15 Reserved */
483487
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
484-
/* Event Types 3 events - 0x16 Dcache read miss count */
488+
/* Event Types 3 events - 0x16 BTB read count */
485489
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
486-
/* Event Types 3 events - 0x17 L2-Cache prefetch hit count */
490+
/* Event Types 3 events - 0x17 BTB read miss count */
487491
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
488-
/* Event Types 3 events - 0x18 DTLB read miss count */
489-
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>;
492+
/* Event Types 3 events - 0x18 BTB write count */
493+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>,
494+
/* Event Types 3 events - 0x19 BTB write miss count */
495+
<0x00000000 0x00000193 0xffffffff 0xffffffff 0x00000078>;
490496
};
491497

492498
clint0: clint@18031000 {

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