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fanghuaqifanghuaqi
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conf/evalsoc: fix pmu event mappings to match corrected nmsis_bench.h
Align the riscv,pmu node event-to-mhpmevent and raw-event-to-mhpmcounters mappings with the corrected performance monitor event definitions in NMSIS nmsis_bench.h (see nuclei-sdk commit da74dcb): - Move ICACHE_PREFETCH_MISS from incorrect Type 3 idx 9 (sel=3, 0x93) to correct Type 1 idx 6 (sel=1, 0x61) per ISA manual errata. - Fix scrambled raw event comments for Event Types 2/3 and add the missing Type 0 idx 0 (Dcache read) / Type 3 idx 25 (BTB write miss) raw event entries so the table matches the actual event encoding. - Add VPU commit events (Type 2, idx 4-7): total/load/store/ computational instruction commit counts (0x42/0x52/0x62/0x72). Signed-off-by: Huaqi Fang <578567190@qq.com> (cherry picked from commit 7d6b139)
1 parent 8abc087 commit b7e7183

4 files changed

Lines changed: 160 additions & 136 deletions

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‎conf/evalsoc/nuclei_rv32imac.dts‎

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -261,8 +261,8 @@
261261
<0x10009 0x00000000 0x00000011>,
262262
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
263263
<0x1000C 0x00000000 0x00000083>,
264-
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=9 Icache prefetch miss count */
265-
<0x1000D 0x00000000 0x00000093>,
264+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=1 idx=6 Icache prefetch miss count */
265+
<0x1000D 0x00000000 0x00000061>,
266266
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
267267
<0x10010 0x00000000 0x000000A3>,
268268
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
@@ -385,7 +385,7 @@
385385
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
386386
/* Event Types 1 events - 0x5 Main TLB miss count */
387387
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
388-
/* Event Types 1 events - 0x6 Reserved */
388+
/* Event Types 1 events - 0x6 Icache prefetch miss count */
389389
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
390390
/* Event Types 1 events - 0x7 Reserved */
391391
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
@@ -401,64 +401,70 @@
401401
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
402402
/* Event Types 1 events - 0xd Timer count */
403403
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
404-
/* Event Types 2 events - 0x1 VPU store instruction commit count */
405-
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00000078>,
406-
/* Event Types 2 events - 0x2 Reserved */
404+
/* Event Types 2 events - 0x2 Branch instruction commit count */
407405
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
408-
/* Event Types 2 events - 0x3 VPU load instruction commit count */
406+
/* Event Types 2 events - 0x3 Branch predict fail count */
409407
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
410-
/* Event Types 2 events - 0x4 VPU computational instruction commit count */
408+
/* Event Types 2 events - 0x4 VPU total instruction commit count */
411409
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
412-
/* Event Types 2 events - 0x5 Branch predict fail count */
410+
/* Event Types 2 events - 0x5 VPU load instruction commit count */
413411
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
414-
/* Event Types 3 events - 0x1 Icache read count */
412+
/* Event Types 2 events - 0x6 VPU store instruction commit count */
413+
<0x00000000 0x00000062 0xffffffff 0xffffffff 0x00000078>,
414+
/* Event Types 2 events - 0x7 VPU computational instruction commit count */
415+
<0x00000000 0x00000072 0xffffffff 0xffffffff 0x00000078>,
416+
/* Event Types 3 events - 0x0 Dcache read count */
417+
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000078>,
418+
/* Event Types 3 events - 0x1 Dcache read miss count */
415419
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
416-
/* Event Types 3 events - 0x2 L2-Cache read hit count */
420+
/* Event Types 3 events - 0x2 Dcache write count */
417421
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
418-
/* Event Types 3 events - 0x3 DTLB write count */
422+
/* Event Types 3 events - 0x3 Dcache write miss count */
419423
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
420-
/* Event Types 3 events - 0x4 L2-Cache write miss count */
424+
/* Event Types 3 events - 0x4 Dcache prefetch count */
421425
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
422-
/* Event Types 3 events - 0x5 Reserved */
426+
/* Event Types 3 events - 0x5 Dcache prefetch miss count */
423427
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
424-
/* Event Types 3 events - 0x6 Icache prefetch miss count */
428+
/* Event Types 3 events - 0x6 Icache read count */
425429
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
426-
/* Event Types 3 events - 0x7 BTB write count */
430+
/* Event Types 3 events - 0x7 Reserved */
427431
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
428-
/* Event Types 3 events - 0x8 L2-Cache read miss count */
432+
/* Event Types 3 events - 0x8 Icache prefetch count */
429433
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
430-
/* Event Types 3 events - 0x9 DTLB write miss count */
434+
/* Event Types 3 events - 0x9 Reserved */
431435
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
432-
/* Event Types 3 events - 0xa ITLB read count */
436+
/* Event Types 3 events - 0xa L2-Cache read count */
433437
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
434-
/* Event Types 3 events - 0xb BTB read count */
438+
/* Event Types 3 events - 0xb L2-Cache read miss count */
435439
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
436-
/* Event Types 3 events - 0xc Dcache prefetch count */
440+
/* Event Types 3 events - 0xc L2-Cache write count */
437441
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
438-
/* Event Types 3 events - 0xd Icache prefetch count */
442+
/* Event Types 3 events - 0xd L2-Cache write miss count */
439443
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
440-
/* Event Types 3 events - 0xe Dcache write count */
444+
/* Event Types 3 events - 0xe L2-Cache prefetch hit count */
441445
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
442-
/* Event Types 3 events - 0xf DTLB read count */
446+
/* Event Types 3 events - 0xf L2-Cache prefetch miss count */
443447
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
444-
/* Event Types 3 events - 0x10 Dcache write miss count */
448+
/* Event Types 3 events - 0x10 DTLB read count */
445449
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
446-
/* Event Types 3 events - 0x11 BTB write miss count */
450+
/* Event Types 3 events - 0x11 DTLB read miss count */
447451
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
448-
/* Event Types 3 events - 0x12 Dcache read count */
452+
/* Event Types 3 events - 0x12 DTLB write count */
449453
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
450-
/* Event Types 3 events - 0x13 L2-Cache write hit count */
454+
/* Event Types 3 events - 0x13 DTLB write miss count */
451455
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
452-
/* Event Types 3 events - 0x14 L2-Cache prefetch miss count */
456+
/* Event Types 3 events - 0x14 ITLB read count */
453457
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
454-
/* Event Types 3 events - 0x15 BTB read miss count */
458+
/* Event Types 3 events - 0x15 Reserved */
455459
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
456-
/* Event Types 3 events - 0x16 Dcache read miss count */
460+
/* Event Types 3 events - 0x16 BTB read count */
457461
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
458-
/* Event Types 3 events - 0x17 L2-Cache prefetch hit count */
462+
/* Event Types 3 events - 0x17 BTB read miss count */
459463
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
460-
/* Event Types 3 events - 0x18 DTLB read miss count */
461-
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>;
464+
/* Event Types 3 events - 0x18 BTB write count */
465+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>,
466+
/* Event Types 3 events - 0x19 BTB write miss count */
467+
<0x00000000 0x00000193 0xffffffff 0xffffffff 0x00000078>;
462468
};
463469

464470
plic0: interrupt-controller@1c000000 {

‎conf/evalsoc/nuclei_rv32imafdc.dts‎

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -261,8 +261,8 @@
261261
<0x10009 0x00000000 0x00000011>,
262262
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
263263
<0x1000C 0x00000000 0x00000083>,
264-
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=9 Icache prefetch miss count */
265-
<0x1000D 0x00000000 0x00000093>,
264+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=1 idx=6 Icache prefetch miss count */
265+
<0x1000D 0x00000000 0x00000061>,
266266
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
267267
<0x10010 0x00000000 0x000000A3>,
268268
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
@@ -385,7 +385,7 @@
385385
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
386386
/* Event Types 1 events - 0x5 Main TLB miss count */
387387
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
388-
/* Event Types 1 events - 0x6 Reserved */
388+
/* Event Types 1 events - 0x6 Icache prefetch miss count */
389389
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
390390
/* Event Types 1 events - 0x7 Reserved */
391391
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
@@ -401,64 +401,70 @@
401401
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
402402
/* Event Types 1 events - 0xd Timer count */
403403
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
404-
/* Event Types 2 events - 0x1 VPU store instruction commit count */
405-
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00000078>,
406-
/* Event Types 2 events - 0x2 Reserved */
404+
/* Event Types 2 events - 0x2 Branch instruction commit count */
407405
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
408-
/* Event Types 2 events - 0x3 VPU load instruction commit count */
406+
/* Event Types 2 events - 0x3 Branch predict fail count */
409407
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
410-
/* Event Types 2 events - 0x4 VPU computational instruction commit count */
408+
/* Event Types 2 events - 0x4 VPU total instruction commit count */
411409
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
412-
/* Event Types 2 events - 0x5 Branch predict fail count */
410+
/* Event Types 2 events - 0x5 VPU load instruction commit count */
413411
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
414-
/* Event Types 3 events - 0x1 Icache read count */
412+
/* Event Types 2 events - 0x6 VPU store instruction commit count */
413+
<0x00000000 0x00000062 0xffffffff 0xffffffff 0x00000078>,
414+
/* Event Types 2 events - 0x7 VPU computational instruction commit count */
415+
<0x00000000 0x00000072 0xffffffff 0xffffffff 0x00000078>,
416+
/* Event Types 3 events - 0x0 Dcache read count */
417+
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000078>,
418+
/* Event Types 3 events - 0x1 Dcache read miss count */
415419
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
416-
/* Event Types 3 events - 0x2 L2-Cache read hit count */
420+
/* Event Types 3 events - 0x2 Dcache write count */
417421
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
418-
/* Event Types 3 events - 0x3 DTLB write count */
422+
/* Event Types 3 events - 0x3 Dcache write miss count */
419423
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
420-
/* Event Types 3 events - 0x4 L2-Cache write miss count */
424+
/* Event Types 3 events - 0x4 Dcache prefetch count */
421425
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
422-
/* Event Types 3 events - 0x5 Reserved */
426+
/* Event Types 3 events - 0x5 Dcache prefetch miss count */
423427
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
424-
/* Event Types 3 events - 0x6 Icache prefetch miss count */
428+
/* Event Types 3 events - 0x6 Icache read count */
425429
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
426-
/* Event Types 3 events - 0x7 BTB write count */
430+
/* Event Types 3 events - 0x7 Reserved */
427431
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
428-
/* Event Types 3 events - 0x8 L2-Cache read miss count */
432+
/* Event Types 3 events - 0x8 Icache prefetch count */
429433
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
430-
/* Event Types 3 events - 0x9 DTLB write miss count */
434+
/* Event Types 3 events - 0x9 Reserved */
431435
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
432-
/* Event Types 3 events - 0xa ITLB read count */
436+
/* Event Types 3 events - 0xa L2-Cache read count */
433437
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
434-
/* Event Types 3 events - 0xb BTB read count */
438+
/* Event Types 3 events - 0xb L2-Cache read miss count */
435439
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
436-
/* Event Types 3 events - 0xc Dcache prefetch count */
440+
/* Event Types 3 events - 0xc L2-Cache write count */
437441
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
438-
/* Event Types 3 events - 0xd Icache prefetch count */
442+
/* Event Types 3 events - 0xd L2-Cache write miss count */
439443
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
440-
/* Event Types 3 events - 0xe Dcache write count */
444+
/* Event Types 3 events - 0xe L2-Cache prefetch hit count */
441445
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
442-
/* Event Types 3 events - 0xf DTLB read count */
446+
/* Event Types 3 events - 0xf L2-Cache prefetch miss count */
443447
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
444-
/* Event Types 3 events - 0x10 Dcache write miss count */
448+
/* Event Types 3 events - 0x10 DTLB read count */
445449
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
446-
/* Event Types 3 events - 0x11 BTB write miss count */
450+
/* Event Types 3 events - 0x11 DTLB read miss count */
447451
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
448-
/* Event Types 3 events - 0x12 Dcache read count */
452+
/* Event Types 3 events - 0x12 DTLB write count */
449453
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
450-
/* Event Types 3 events - 0x13 L2-Cache write hit count */
454+
/* Event Types 3 events - 0x13 DTLB write miss count */
451455
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
452-
/* Event Types 3 events - 0x14 L2-Cache prefetch miss count */
456+
/* Event Types 3 events - 0x14 ITLB read count */
453457
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
454-
/* Event Types 3 events - 0x15 BTB read miss count */
458+
/* Event Types 3 events - 0x15 Reserved */
455459
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
456-
/* Event Types 3 events - 0x16 Dcache read miss count */
460+
/* Event Types 3 events - 0x16 BTB read count */
457461
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
458-
/* Event Types 3 events - 0x17 L2-Cache prefetch hit count */
462+
/* Event Types 3 events - 0x17 BTB read miss count */
459463
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
460-
/* Event Types 3 events - 0x18 DTLB read miss count */
461-
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>;
464+
/* Event Types 3 events - 0x18 BTB write count */
465+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>,
466+
/* Event Types 3 events - 0x19 BTB write miss count */
467+
<0x00000000 0x00000193 0xffffffff 0xffffffff 0x00000078>;
462468
};
463469

464470
plic0: interrupt-controller@1c000000 {

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