SoC/evalsoc: enable SMP ENB after L2 Cache enable for SMP/IOCP consistency

Write 0xFFFFFFFF to SMPCC SMP_ENB register (offset 0xC) after L2 Cache
enable in both __sync_harts() and _premain_init() to ensure SMP and
IOCP consistency across cluster cores before other SMP operations.

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

SoC/evalsoc/Common/Source/system_evalsoc.c

@@ -1344,7 +1344,7 @@ void __sync_harts(void)
             SMP_CTRLREG(smp_base, 0x10) |= 0x1;
             SMP_CTRLREG(smp_base, 0xd8) = 0x0;
         }
-        // Enable SMP
+        // Enable SMP and IOCP consistency
         SMP_CTRLREG(smp_base, 0xc) = 0xFFFFFFFF;
         __SMP_RWMB();
         // L1 I/D Cache Enable is done in _premain_init
@@ -1571,14 +1571,15 @@ void _premain_init(void)
         // Enable L2, disable cluster local memory
         SMP_CTRLREG(__SMPCC_BASEADDR, 0x10) |= 0x1;
         SMP_CTRLREG(__SMPCC_BASEADDR, 0xd8) = 0x0;
-        __SMP_RWMB();
 #else
         // Disable L2, enable cluster local memory
         SMP_CTRLREG(__SMPCC_BASEADDR, 0x10) &= ~0x1;
         // use as clm or cache, when l2 disable, the affect to ddr is the same, l2 is really disabled
         SMP_CTRLREG(__SMPCC_BASEADDR, 0xd8) = 0;//0xFFFFFFFF;
-        __SMP_RWMB();
 #endif
+        // Enable SMP and IOCP consistency
+        SMP_CTRLREG(__SMPCC_BASEADDR, 0xC) = 0xFFFFFFFF;
+        __SMP_RWMB();
     }
 
 #if defined(RUNMODE_BPU_EN)

doc/source/changelog.rst

@@ -12,6 +12,7 @@ This is release version of ``1.0.0`` of Nuclei SDK, which is still under develop
 
   - Warn when ``CFG_IREGION_BASE_ADDR`` is defined as ``0`` and document the required compiler option.
   - Fix EvalSoC UART stop-bit and FIFO watermark configuration to update the intended control-register fields.
+  - Enable SMP_ENB register of SMPCC with ``0xFFFFFFFF`` after L2 Cache enable to ensure SMP and IOCP consistency across cluster cores in ``system_evalsoc.c``.
 
 V0.9.0
 ------