OS/ThreadX: Fix SMP IRQ system state handling and IRQ-exit reschedule

Update the Nuclei SMP interrupt entry paths to maintain
`_tx_thread_system_state` per hart for normal IRQ nesting, while keeping
the scheduler SWI path separate. This lets ThreadX caller checks
correctly detect IRQ context, so illegal system calls made from timer
or interrupt context are rejected instead of running into normal
thread-side scheduling paths and faulting later.

Also add an non-vector IRQ-exit scheduling check that raises the local
scheduler SWI only after IRQ nesting unwinds back to thread context, when
the current thread no longer matches the execute slot and preemption is
enabled. Apply the same behavior to both GCC and IAR ports.

This change only updates the common non-vector IRQ exit path.
If a vector interrupt path also needs IRQ-exit reschedule behavior, it
should invoke `_tx_thread_irq_exit_schedule_check` before returning to
thread context.

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

OS/ThreadX/ports_smp/nuclei/gcc/interrupt.S

@@ -1,6 +1,8 @@
 #include "riscv_encoding.h"
 #include "cpufeature.h"
 
+    .extern _tx_thread_irq_exit_schedule_check
+
 .section    .text.entry
 .align 8
 
@@ -15,6 +17,19 @@
     csrc CSR_MSTATUS, MSTATUS_MIE
 .endm
 
+/* Update ThreadX SMP per-core ISR nesting state.
+ * This macro must be called after SAVE_CONTEXT because it clobbers t0-t2.
+ */
+.macro UPDATE_THREADX_SYSTEM_STATE delta
+    la t0, _tx_thread_system_state
+    csrr t1, CSR_MHARTID
+    slli t1, t1, LOG_REGBYTES
+    add t0, t0, t1
+    LOAD t2, 0(t0)
+    addi t2, t2, \delta
+    STORE t2, 0(t0)
+.endm
+
 /**
  * \brief  Macro for context save
  * \details
@@ -202,6 +217,11 @@ irq_entry:
     /* Save the necessary CSR registers */
     SAVE_CSR_CONTEXT
 
+    /* Mark this core as being in a normal IRQ handler.
+     * eclic_msip_handler is the scheduler SWI path and is handled separately.
+     */
+    UPDATE_THREADX_SYSTEM_STATE 1
+
     /* This special CSR read/write operation, which is actually
      * claim the CLIC to find its pending highest ID, if the ID
      * is not 0, then automatically enable the mstatus.MIE, and
@@ -212,6 +232,17 @@ irq_entry:
     /* Critical section with interrupts disabled */
     DISABLE_MIE
 
+    /* All nested IRQ work claimed by JALMNXTI is done; leave ThreadX ISR context
+     * before restoring the interrupted context.
+     */
+    UPDATE_THREADX_SYSTEM_STATE -1
+
+    /* If ThreadX is about to return to normal thread context and the
+     * scheduler already selected a different execute thread for this core,
+     * request the scheduler SWI now.
+     */
+    call _tx_thread_irq_exit_schedule_check
+
     /* Restore the necessary CSR registers */
     RESTORE_CSR_CONTEXT
     /* Restore the caller saving registers (context) */

OS/ThreadX/ports_smp/nuclei/iar/interrupt.S

@@ -5,6 +5,19 @@ DISABLE_MIE MACRO
   csrci CSR_MSTATUS, MSTATUS_MIE
   ENDM
 
+/* Update ThreadX SMP per-core ISR nesting state.
+ * This macro must be called after SAVE_CONTEXT because it clobbers t0-t2.
+ */
+UPDATE_THREADX_SYSTEM_STATE MACRO delta
+    la t0, _tx_thread_system_state
+    csrr t1, CSR_MHARTID
+    slli t1, t1, LOG_REGBYTES
+    add t0, t0, t1
+    LOAD t2, 0(t0)
+    addi t2, t2, delta
+    STORE t2, 0(t0)
+  ENDM
+
 SAVE_CONTEXT MACRO
 #if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
 #else
@@ -97,6 +110,8 @@ RESTORE_CSR_CONTEXT MACRO
     PUBLIC exc_entry, irq_entry, default_intexc_handler
     PUBLIC Undef_Handler
     EXTERN core_exception_handler
+    EXTERN _tx_thread_irq_exit_schedule_check
+    EXTERN _tx_thread_system_state
     SECTION `.text`:CODE:NOROOT(2)
     CODE
 
@@ -162,6 +177,11 @@ irq_entry:
     /* Save the necessary CSR registers */
     SAVE_CSR_CONTEXT
 
+    /* Mark this core as being in a normal IRQ handler.
+     * eclic_msip_handler is the scheduler SWI path and is handled separately.
+     */
+    UPDATE_THREADX_SYSTEM_STATE 1
+
     /* This special CSR read/write operation, which is actually
      * claim the CLIC to find its pending highest ID, if the ID
      * is not 0, then automatically enable the mstatus.MIE, and
@@ -172,6 +192,17 @@ irq_entry:
     /* Critical section with interrupts disabled */
     DISABLE_MIE
 
+    /* All nested IRQ work claimed by JALMNXTI is done; leave ThreadX ISR context
+     * before restoring the interrupted context.
+     */
+    UPDATE_THREADX_SYSTEM_STATE -1
+
+    /* If ThreadX is about to return to normal thread context and the
+     * scheduler already selected a different execute thread for this core,
+     * request the scheduler SWI now.
+     */
+    call _tx_thread_irq_exit_schedule_check
+
     /* Restore the necessary CSR registers */
     RESTORE_CSR_CONTEXT
     /* Restore the caller saving registers (context) */

OS/ThreadX/ports_smp/nuclei/port.c

@@ -267,6 +267,35 @@ void _tx_thread_smp_core_preempt(UINT core)
     within the specified behaviour for the architecture. */
     __RWMB();
 }
+
+void _tx_thread_irq_exit_schedule_check(void)
+{
+    UINT coreid;
+
+    coreid = _tx_thread_smp_core_get();
+
+    /* Only request scheduling when the IRQ nesting for this core has fully
+       unwound and ThreadX is about to return to normal thread context. */
+    if (_tx_thread_system_state[coreid] != ((ULONG)0)) {
+        return;
+    }
+
+    /* No scheduling request is needed if the current thread already matches
+       the scheduler's execute target for this core. */
+    if (_tx_thread_current_ptr[coreid] == _tx_thread_execute_ptr[coreid]) {
+        return;
+    }
+
+    /* Honor ThreadX global preemption disable state.  If scheduling is
+       deferred here, the normal ThreadX resume/preempt paths are expected
+       to request it later. */
+    if (_tx_thread_preempt_disable != ((UINT)0)) {
+        return;
+    }
+
+    SysTimer_SetSWIRQ();
+    __RWMB();
+}
 #endif
 
 // _tx_thread_schedule function implemented in context.S