NMSIS/Core: fix performance monitor event definitions in nmsis_bench.h

Move ICACHE_PREFETCH_MISS from incorrect Type 3 idx 9 to correct
Type 1 idx 6 according to ISA manual errata, and add VPU commit
event definitions (Type 2, idx 4-7).

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

NMSIS/Core/Include/nmsis_bench.h

@@ -289,6 +289,7 @@ __STATIC_FORCEINLINE void __prepare_bench_env(void)
 #define EVENT_TYPE_1_ITLB_READ_MISS                                             3
 #define EVENT_TYPE_1_DTLB_RW_MISS                                               4
 #define EVENT_TYPE_1_MAIN_TLB_MISS                                              5
+#define EVENT_TYPE_1_ICACHE_PREFETCH_MISS                                       6
 #define EVENT_TYPE_1_L2_CACHE_ACCESS                                            8
 #define EVENT_TYPE_1_L2_CACHE_MISS                                              9
 #define EVENT_TYPE_1_MEMORY_BUS_REQUEST                                         10
@@ -299,6 +300,10 @@ __STATIC_FORCEINLINE void __prepare_bench_env(void)
 /* Events Type 2 (event sel == 2) event name macros */
 #define EVENT_TYPE_2_BRANCH_INSTRUCTION_COMMIT                                  2
 #define EVENT_TYPE_2_BRANCH_PREDICT_FAIL_COMMIT                                 3
+#define EVENT_TYPE_2_VPU_TOTAL_INSTRUCTION_COMMIT                               4
+#define EVENT_TYPE_2_VPU_LOAD_INSTRUCTION_COMMIT                                5
+#define EVENT_TYPE_2_VPU_STORE_INSTRUCTION_COMMIT                               6
+#define EVENT_TYPE_2_VPU_COMPUTATIONAL_INSTRUCTION_COMMIT                       7
 
 /* Events Type 3 (event sel == 3) event name macros */
 #define EVENT_TYPE_3_DCACHE_READ                                                0
@@ -309,7 +314,6 @@ __STATIC_FORCEINLINE void __prepare_bench_env(void)
 #define EVENT_TYPE_3_DCACHE_PREFETCH_MISS                                       5
 #define EVENT_TYPE_3_ICACHE_READ                                                6
 #define EVENT_TYPE_3_ICACHE_PREFETCH                                            8
-#define EVENT_TYPE_3_ICACHE_PREFETCH_MISS                                       9
 #define EVENT_TYPE_3_L2_CACHE_READ                                              10
 #define EVENT_TYPE_3_L2_CACHE_READ_MISS                                         11
 #define EVENT_TYPE_3_L2_CACHE_WRITE                                             12

doc/source/changelog.rst

@@ -14,6 +14,10 @@ This is release version of ``1.0.0`` of Nuclei SDK, which is still under develop
   - Fix EvalSoC UART stop-bit and FIFO watermark configuration to update the intended control-register fields.
   - Reorder ``_premain_init()`` cache initialization in ``system_evalsoc.c``: L2 Cache and SMP/IOCP EN are now initialized before L1 I/D Cache to ensure correct SMP coherency setup sequence.
 
+* NMSIS
+
+  - Correct performance monitor event definitions in ``nmsis_bench.h``: move ``ICACHE_PREFETCH_MISS`` from Type 3 idx 9 to correct position Type 1 idx 6 per ISA manual errata, and add VPU commit event definitions (Type 2, idx 4-7).
+
 V0.9.0
 ------