OS/ThreadX: fix TX_DISABLE/TX_RESTORE macros with volatile and memory clobber

Add volatile keyword and memory clobber to inline assembly in `TX_DISABLE`
and `TX_RESTORE` macros to prevent compiler reordering and ensure proper
memory barrier semantics for interrupt disable/restore operations.

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

OS/ThreadX/ports/nuclei/tx_port.h

@@ -296,10 +296,10 @@ typedef unsigned short                          USHORT;
 
 #define TX_INTERRUPT_SAVE_AREA                  ULONG interrupt_save;
 /* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus.  */
-#define TX_DISABLE                              {__asm__ ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : );};
+#define TX_DISABLE                              {__asm__ volatile ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : : "memory");};
 /* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus.  */
 #define TX_RESTORE                              {register ULONG __tempmask = interrupt_save & 0x08; \
-                                                __asm__ ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : );};
+                                                __asm__ volatile ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : "memory");};
 
 #endif
 

doc/source/changelog.rst

@@ -125,6 +125,7 @@ This is release version of ``0.9.0`` of Nuclei SDK, which is still under develop
   - Fix RT-Thread and UCOSII interrupt masking implementation in ``cpuport.c`` and ``os_cpu_port.h`` to add memory barriers after CSR operations, ensuring pending interrupts are properly handled after enabling interrupts
   - Fix FreeRTOS tickless sleep mode by removing unnecessary ``__FENCE_I()`` call in ``vPortSuppressTicksAndSleep`` function to avoid i-cache misses and reduce interrupt latency. The ``__RWMB()`` memory barrier is sufficient for proper interrupt enable propagation
   - Upgrade FreeRTOS to v11.2.0 and update porting layer to match new API requirements (critical nesting macros and recursive lock functions now accept core ID parameter for SMP systems)
+  - Fix ThreadX ``tx_port.h`` interrupt disable/restore macros (``TX_DISABLE``/``TX_RESTORE``) by adding ``volatile`` keyword and ``memory`` clobber to inline assembly to prevent compiler reordering and ensure proper memory barrier semantics
 
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