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- #4556 · NewPaulWalker opened
on Apr 14, 2025 1 - #4242 · castleberrysam opened
on Feb 2, 2025 11
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[Bug] large PlatformGrain values truncate PMP/PMA generator masks
module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6456 In OpenXiangShan/XiangShan;[Bug] MPT permission level can shrink the TLB SFENCE match range
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6455 In OpenXiangShan/XiangShan;[Bug] MMPT context changes do not invalidate all retained MPT state
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6454 In OpenXiangShan/XiangShan;[Bug] MPT table reads are issued before PMP/PMA denial is applied
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6453 In OpenXiangShan/XiangShan;[Bug] AMOCAS.Q STA uops can collide at the single AtomicsUnit input
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanmodule: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6452 In OpenXiangShan/XiangShan;[Bug] TIMER allows MaxHartIdBits to overlap mtimecmp with mtime
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6451 In OpenXiangShan/XiangShan;TopDownCounters object refactoring thoughts
topic: code qualityTo make code more readable & maintainableTo make code more readable & maintainabletopic: verificationTo make function/performance verification easierTo make function/performance verification easierStatus: Open.#6427 In OpenXiangShan/XiangShan;[Bug] dcsr.stopcount=1 does not stop minstret/mcycle in Debug Mode; only the instret/cycle read values are frozen
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedtype: feature/planned(issue) Feature requests that are accepted/planned(issue) Feature requests that are accepted/plannedStatus: Open.#6419 In OpenXiangShan/XiangShan;- Status: Open.#6410 In OpenXiangShan/XiangShan;
Vector load doesn't trigger illegal instruction trap when VSEW is invalid
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6407 In OpenXiangShan/XiangShan;[Bug] ICache: a TileLink error on one fetch request's cache line raises an instruction access fault on the other request
module: frontendBpu, Ftq, Ifu, ICache, IBufferBpu, Ftq, Ifu, ICache, IBuffertype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedStatus: Open.#6404 In OpenXiangShan/XiangShan;mtvalmismatch on scalar store access fault after a vector store access faultmodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanmodule: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedStatus: Open.#6399 In OpenXiangShan/XiangShan;