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RSX: Fix SAT and ABS order #19326

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Merged
kd-11 merged 2 commits into from
Aug 31, 2026
+10 −1
Merged

RSX: Fix SAT and ABS order #19326

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b83d9c7
twistedmetal2
Yahfz Aug 29, 2026
03a39f5
Merge branch 'master' into twistedmetal
kd-11 Aug 31, 2026
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4 changes: 3 additions & 1 deletion rpcs3/Emu/RSX/Program/FragmentProgramDecompiler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -792,8 +792,10 @@ template<typename T> std::string FragmentProgramDecompiler::GetSRC(T src)
}

// Warning: Modifier order matters. e.g neg should be applied after precision clamping (tested with Naruto UNS)
const bool precision_before_abs = precision_modifier == RSX_FP_PRECISION_SATURATE;
if (precision_before_abs) ret = ClampValue(ret, precision_modifier);
if (src.abs) ret = "abs(" + ret + ")";
if (precision_modifier) ret = ClampValue(ret, precision_modifier);
if (precision_modifier && !precision_before_abs) ret = ClampValue(ret, precision_modifier);
if (src.neg) ret = "-" + ret;

return ret;
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7 changes: 7 additions & 0 deletions rpcs3/Emu/RSX/Program/GLSLInterpreter/FragmentInterpreter.glsl
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Expand Up @@ -83,6 +83,8 @@ layout(location=0) in vec4 in_regs[16];
#define RSX_FP_REGISTER_TYPE_CONSTANT 2
#define RSX_FP_REGISTER_TYPE_UNKNOWN 3

#define RSX_FP_PRECISION_SATURATE 4

#define CELL_GCM_SHADER_CONTROL_DEPTH_EXPORT 0xe
#define CELL_GCM_SHADER_CONTROL_32_BITS_EXPORTS 0x40

Expand Down Expand Up @@ -242,6 +244,11 @@ vec4 read_src(const in int index)
ur1 = GET_INST_BITS(index + 1, 9, 8);
vr0 = shuffle(vr0, ur1);

if (GET_INST_BITS(2, 19 + index * 3, 3) == RSX_FP_PRECISION_SATURATE)
{
vr0 = clamp(select(vr0, vr_zero, isnan(vr0)), 0., 1.);
}

// abs
if (index == 0)
{
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