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fix(linker): correct cross-toolchain memory map inconsistencies #21

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fix(linker): correct cross-toolchain memory map inconsistencies in ST…
94xhn Jul 11, 2026
d7bdc94
Align reviewed linker maps with the confirmed AXISRAM boundaries
94xhn Jul 28, 2026
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2 changes: 1 addition & 1 deletion ...RTEX/CORTEX_InterruptSwitch_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ _Min_Stack_Size = 0x1000; /* required amount of stack */
/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = 0x241a0000, LENGTH = 256K
RAM (xrw) : ORIGIN = 0x241a0000, LENGTH = 384K

@ALABSTM ALABSTM Jul 27, 2026

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Strange that the memory is not split between ROM and RAM as done for the two other IDEs. It is the case in a similar application, as shown below.

STM32CubeN6/Projects/NUCLEO-N657X0-Q/Applications/ThreadX/Tx_SecureLEDToggle_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_LRUN.ld

Lines 47 to 48 in 8ab3b64

ROM (xrw) : ORIGIN = 0x24100400, LENGTH = 511K
RAM (xrw) : ORIGIN = 0x24180000, LENGTH = 512K

@94xhn 94xhn Jul 28, 2026

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Thanks, I aligned the GCC script with that split now. The non-secure window is defined as ROM 0x241A0000-0x241BFFFF plus RAM 0x241C0000-0x241FFFFF, matching the example's IAR file, MDK scatter file, and README.

}

/* Sections */
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2 changes: 1 addition & 1 deletion ...6570-DK/Applications/VENC/VENC_RTSP_Server/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K
DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K
}

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2 changes: 1 addition & 1 deletion Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld
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Expand Up @@ -48,7 +48,7 @@ _eDTCM = ORIGIN(DTCM) + LENGTH(DTCM);
/* Memories definition */
MEMORY
{
ROM (xr) : ORIGIN = 0x34000400, LENGTH = 256K
ROM (xr) : ORIGIN = 0x34000400, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341B7000, LENGTH = 2340K
DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K
}
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2 changes: 1 addition & 1 deletion ...TM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K
DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K
}

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2 changes: 1 addition & 1 deletion ...0-DK/Applications/VENC/VENC_SDCard_ThreadX/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K
DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K
}

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2 changes: 1 addition & 1 deletion ...s/STM32N6570-DK/Applications/VENC/VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K
RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K
DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K
}

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2 changes: 1 addition & 1 deletion Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xrw) : ORIGIN = 0x34000400, LENGTH = 511K
RAM (xrw) : ORIGIN = 0x34020000, LENGTH = 1536K
RAM (xrw) : ORIGIN = 0x34080000, LENGTH = 1536K

@ALABSTM ALABSTM Jul 27, 2026

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I am also questioning the length of this memory area in secure AXISRAM1. 1536kB in decimal translate to 0x0018'0000B in hexadecimal, making this region extend till address 0x341F'FFFF.

This overlaps with the FSBL in secure AXISRAM2, starting at address 0x3418'0000 according to the REAMD.md (see below), assuming both memories are contiguous. Does it not?

According to Table 2. Memory map and peripheral register boundary addresses of RM0486, rev. 4, the secure AXISRAM1 region ends at address 0x340F'FFFF. This would leave only 512kB room for the RAM region.

STM32CubeN6/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/README.md

Lines 13 to 14 in 8ab3b64

- The FSBL project runs in AXISRAM2 (0x3418'0000) and is executed upon power-on after bootROM execution.
- The application is loaded into AXISRAM1 (0x3400'0000) and executed after the FSBL.

@94xhn 94xhn Jul 28, 2026

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Hi @ALABSTM, you were right here. I rechecked the example-specific MDK scatter file and the RAM window for this PWR application is 0x34080000-0x340FFFFF, not 1536KB up to 0x341FFFFF. I have now updated both GCC and IAR for PWR_STANDBY and PWR_STANDBY_RTC to the same 512KB range, which also removes the overlap with the FSBL in AXISRAM2.

@ALABSTM ALABSTM Jul 28, 2026

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Hi @94xhn,

I built the Appli subproject of the PWR_STANDBY example using STM32CubeIDE 2.1.1 and, based on the log, the footprint of the different sections to be located into the RAM region is just a "handful" of bytes, confirming the 512kB length fix.

arm-none-eabi-objcopy  -O binary PWR_STANDBY_Appli.elf  "PWR_STANDBY_Appli.bin"
   text	   data	    bss	    dec	    hex	filename
  14312	     32	   2592	  16936	   4228	PWR_STANDBY_Appli.elf
Finished building: default.size.stdout

With regards,

@94xhn 94xhn Jul 28, 2026

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Thank you for checking it with STM32CubeIDE and for the approval. That build result is useful confirmation of the corrected RAM range.

}

/* Sections */
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2 changes: 1 addition & 1 deletion ...ects/STM32N6570-DK/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */
MEMORY
{
ROM (xrw) : ORIGIN = 0x34000400, LENGTH = 511K
RAM (xrw) : ORIGIN = 0x34020000, LENGTH = 1536K
RAM (xrw) : ORIGIN = 0x34080000, LENGTH = 1536K

@ALABSTM ALABSTM Jul 27, 2026

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Same remark about the RAM region's length.

@94xhn 94xhn Jul 28, 2026

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Applied the same correction to the RTC sibling as well: GCC and IAR now both use RAM 0x34080000-0x340FFFFF, matching the MDK scatter file there too.

}

/* Sections */
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