Implement StdRegister readback

basil/RL/StdRegister.py

@@ -127,7 +127,10 @@ def write(self, size=None):
                 self._drv.start()
 
     def read(self):
-        raise NotImplementedError("read() not implemented")
+        """Read the backing hardware layer and update all named fields."""
+        data = self._drv.get_data()
+        self.frombytes(data)
+        return data
 
     def _construct_reg(self):
         for field in self._fields:

tests/test_StdRegister.py

@@ -6,11 +6,13 @@
 #
 
 import unittest
+from unittest.mock import Mock
 
 import yaml
 from bitarray import bitarray
 
 from basil.dut import Dut
+from basil.RL.StdRegister import StdRegister
 
 cnfg_yaml = """
 transfer_layer:
@@ -76,6 +78,29 @@ def test_mem_bytes(self):
         self.assertEqual(4, self.dut["spi_module"].MEM_BYTES)
         self.assertRaises(ValueError, self.dut["spi_module"].set_data, [1, 2, 3, 4, 5])
 
+    def test_read(self):
+        driver = Mock()
+        data = [0xA5, 0x5A]
+        driver.get_data.return_value = data
+        register = StdRegister(
+            driver,
+            {
+                "name": "READBACK",
+                "size": 16,
+                "fields": [
+                    {"name": "UPPER", "size": 8, "offset": 15},
+                    {"name": "LOWER", "size": 8, "offset": 7},
+                ],
+            },
+        )
+
+        result = register.read()
+
+        driver.get_data.assert_called_once_with()
+        self.assertIs(result, data)
+        self.assertEqual(register["UPPER"].tovalue(), 0xA5)
+        self.assertEqual(register["LOWER"].tovalue(), 0x5A)
+
     def test_init_simple(self):
         self.dut["TEST1"].write()
         mem = dict()