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| 1 | +From cce1965aac147f87bcbdfb31ef993e33704c93fa Mon Sep 17 00:00:00 2001 |
| 2 | +From: Josua Mayer <josua@solid-run.com> |
| 3 | +Date: Wed, 10 Jun 2026 13:20:50 +0200 |
| 4 | +Subject: [PATCH] arm64: dts: lx2160a: avoid 32-bit pcie window system ram |
| 5 | + overlap |
| 6 | + |
| 7 | +A 3GB non-prefetchable PCIe bus window can overlap with inbound DMA |
| 8 | +addresses for low system RAM, so DMA transactions may be routed to a BAR |
| 9 | +on the same host bridge instead of memory. |
| 10 | + |
| 11 | +Change the 32-bit non-prefetchable PCIe window back from 3GB to 1GB on all |
| 12 | +controllers, avoiding that overlap while keeping the added 64-bit |
| 13 | +prefetchable region. |
| 14 | + |
| 15 | +Signed-off-by: Josua Mayer <josua@solid-run.com> |
| 16 | +--- |
| 17 | + arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 12 ++++++------ |
| 18 | + 1 file changed, 6 insertions(+), 6 deletions(-) |
| 19 | + |
| 20 | +diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |
| 21 | +index c589a2bad398..a7eeef48550d 100644 |
| 22 | +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |
| 23 | ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |
| 24 | +@@ -1164,7 +1164,7 @@ pcie1: pcie@3400000 { |
| 25 | + <0x42102200 0x86 0x00000000 0x86 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 26 | + <0x42102200 0x85 0x00000000 0x85 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 27 | + <0x42102200 0x84 0x00000000 0x84 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 28 | +- <0x02000200 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 29 | ++ <0x02000200 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 30 | + <0x01200100 0x00 0x00000000 0x80 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 31 | + msi-parent = <&its>; |
| 32 | + #interrupt-cells = <1>; |
| 33 | +@@ -1197,7 +1197,7 @@ pcie2: pcie@3500000 { |
| 34 | + <0x42102200 0x8e 0x00000000 0x8e 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 35 | + <0x42102200 0x8d 0x00000000 0x8d 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 36 | + <0x42102200 0x8c 0x00000000 0x8c 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 37 | +- <0x02000200 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 38 | ++ <0x02000200 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 39 | + <0x01200100 0x00 0x00000000 0x88 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 40 | + msi-parent = <&its>; |
| 41 | + #interrupt-cells = <1>; |
| 42 | +@@ -1230,7 +1230,7 @@ pcie3: pcie@3600000 { |
| 43 | + <0x42102200 0x96 0x00000000 0x96 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 44 | + <0x42102200 0x95 0x00000000 0x95 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 45 | + <0x42102200 0x94 0x00000000 0x94 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 46 | +- <0x02000200 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 47 | ++ <0x02000200 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 48 | + <0x01200100 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 49 | + msi-parent = <&its>; |
| 50 | + #interrupt-cells = <1>; |
| 51 | +@@ -1263,7 +1263,7 @@ pcie4: pcie@3700000 { |
| 52 | + <0x42102200 0x9e 0x00000000 0x9e 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 53 | + <0x42102200 0x9d 0x00000000 0x9d 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 54 | + <0x42102200 0x9c 0x00000000 0x9c 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 55 | +- <0x02000200 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 56 | ++ <0x02000200 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 57 | + <0x01200100 0x00 0x00000000 0x98 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 58 | + msi-parent = <&its>; |
| 59 | + #interrupt-cells = <1>; |
| 60 | +@@ -1296,7 +1296,7 @@ pcie5: pcie@3800000 { |
| 61 | + <0x42102200 0xa6 0x00000000 0xa6 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 62 | + <0x42102200 0xa5 0x00000000 0xa5 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 63 | + <0x42102200 0xa4 0x00000000 0xa4 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 64 | +- <0x02000200 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 65 | ++ <0x02000200 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 66 | + <0x01200100 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 67 | + msi-parent = <&its>; |
| 68 | + #interrupt-cells = <1>; |
| 69 | +@@ -1329,7 +1329,7 @@ pcie6: pcie@3900000 { |
| 70 | + <0x42102200 0xae 0x00000000 0xae 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 71 | + <0x42102200 0xad 0x00000000 0xad 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 72 | + <0x42102200 0xac 0x00000000 0xac 0x00000000 0x01 0x00000000>, /* 64-Bit - prefetchable - 4GB chunk */ |
| 73 | +- <0x02000200 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */ |
| 74 | ++ <0x02000200 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, /* 32-Bit - non-prefetchable */ |
| 75 | + <0x01200100 0x00 0x00000000 0xa8 0x10000000 0x00 0x00010000>; /* 16-Bit IO Window */ |
| 76 | + msi-parent = <&its>; |
| 77 | + #interrupt-cells = <1>; |
| 78 | +-- |
| 79 | +2.51.0 |
| 80 | + |
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