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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Wed Nov 14 10:41:03 2018
# Process ID: 13508
# Current directory: E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14872 E:\PES UNIVERSITY\SEMESTER 5\CO_Project_ALU\alu\alu.xpr
# Log file: E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/vivado.log
# Journal file: E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.xpr}
update_compile_order -fileset sources_1
close [ open {E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.srcs/sources_1/new/decoder.v} w ]
add_files {{E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.srcs/sources_1/new/decoder.v}}
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
set_property is_enabled false [get_files {{E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.srcs/sources_1/new/decoder.v}}]
update_compile_order -fileset sources_1
launch_simulation
source sim_alu.tcl
close_sim
synth_design -rtl -name rtl_1
launch_simulation
source sim_alu.tcl
close_sim
set_property is_enabled false [get_files {{E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.srcs/sim_1/new/testbench.v}}]
launch_simulation
source alu.tcl
restart
add_force {/alu/A} -radix bin {1010 0ns}
add_force {/alu/B} -radix bin {0101 0ns}
add_force {/alu/A} -radix bin {10101010 0ns}
add_force {/alu/B} -radix hex {01010101 0ns}
add_force {/alu/B} -radix bin {01010101 0ns}
add_force {/alu/Select} -radix bin {0100 0ns}
run 10 us
run 10 us
add_force {/alu/Select} -radix bin {0000 0ns}
run 10 us
add_force {/alu/Select} -radix bin {0101 0ns}
add_force {/alu/Select} -radix hex {1111 0ns}
add_force {/alu/Select} -radix bin {1111 0ns}
add_force {/alu/Select} -radix bin {1110 0ns}
add_force {/alu/Select} -radix bin {1111 0ns}
run 10 us
close_sim
set_property is_enabled true [get_files {{E:/PES UNIVERSITY/SEMESTER 5/CO_Project_ALU/alu/alu.srcs/sim_1/new/testbench.v}}]
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
source sim_alu.tcl
restart
add_force {/sim_alu/A} -radix bin {10101010 0ns}
add_force {/sim_alu/A} -radix bin {10101010 0ns}
close_sim
launch_simulation
source sim_alu.tcl
add_force {/sim_alu/A} -radix bin {10101010 0ns}
add_force {/sim_alu/B} -radix bin {01010101 0ns}
add_force {/sim_alu/Select} -radix bin {0000 0ns}
run all
restart
add_force {/sim_alu/A} -radix bin {10101010 0ns}
add_force {/sim_alu/B} -radix hex {01010101 0ns}
add_force {/sim_alu/B} -radix bin {01010101 0ns}
add_force {/sim_alu/Select} -radix bin {0000 0ns}
run all
run 10 us
restart
add_force {/sim_alu/A} -radix hex {10101010 0ns}
add_force {/sim_alu/A} -radix bin {10101010 0ns}
add_force {/sim_alu/B} -radix bin {01010101 0ns}
add_force {/sim_alu/Select} -radix bin {0000 0ns}
run 10 us
close_sim
launch_simulation
source sim_alu.tcl
add_force {/sim_alu/A} -radix bin {10101010 0ns}
add_force {/sim_alu/B} -radix bin {01010101 0ns}
add_force {/sim_alu/Select} -radix bin {0000 0ns}
run all
close_sim
launch_simulation
source sim_alu.tcl
close_sim