This repository contains TI's TPS929XXX-SALEAE-HLA-DESIGN-TOOL
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This HLA (High Level Analyzer) decodes the FlexWire protocol used by TI LED drivers TPS92912x-Q1, TPS929160-Q1, and TPS929240-Q1. FlexWire is a half-duplex UART-based protocol where a master communicates with up to 16 addressed slaves over a shared bus. The analyzer processes output from the Async Serial (UART) analyzer and annotates each field of every FlexWire frame: sync byte, device address (with R/W, broadcast, and data length), register address, data bytes, and CRC. For non-broadcast commands, the slave response and its CRC are also annotated.
TPS929120-Q1, TPS929121-Q1, TPS929160-Q1, TPS929240-Q1
Add an Async Serial analyzer and configure it for the FlexWire signal:
- Bit Rate: Match the data rate in use (FlexWire supports 10,000 to 1,000,000 bps)
- Bits per Frame: 8
- Stop Bits: 1
- Parity: None
- Significant Bit: LSB First
- Signal Inversion: Non-Inverted
- Mode: Normal
Add a FlexWire HLA analyzer and configure:
- Input Analyzer: Select the Async Serial analyzer created in step 1
- Device Type: Select the target device variant
TPS929120-Q1: DATA_LENGTH field encodes 1 / 2 / 4 / 8 bytesTPS929160/240-Q1: DATA_LENGTH field encodes 1 / 4 / 16 / 24 bytes
- Network Topology: Select the physical layer in use
CAN_PHY(default): CAN transceiver present; slave responses are expected for all non-broadcast commands and will be decodedUART_ONLY: Direct UART connection; no slave response is expected and the state machine returns to IDLE after the command CRC
- ACK Disabled: Set to
Yesif the TPS929160/240-Q1 device has ACK disabled; suppresses response decoding for non-broadcast commands. Has no effect when Device Type is TPS929120-Q1 or Network Topology is UART_ONLY.
Every FlexWire transaction on the bus (master → slave direction) follows this structure:
| Byte | Field | Description |
|---|---|---|
| 1 | SYNC |
Always 0x55; slave uses this to lock its internal clock to the master baud rate |
| 2 | DEV_ADDR |
[7] R/W, [6] BROADCAST, [5:4] DATA_LENGTH, [3:0] DEVICE_ADDR |
| 3 | REG_ADDR |
Target register address (0x00–0xFF) |
| 4…N | DATA |
Write data bytes (absent for read commands); count set by DATA_LENGTH |
| N+1 | CRC |
CRC-8 over DEV_ADDR + REG_ADDR + DATA (SYNC byte excluded) |
For non-broadcast commands the slave replies on the TX line:
| Byte | Field | Description |
|---|---|---|
| 1 | STATUS / RESP |
Write response: STATUS (FLAG0/FLAG_ERR register value); Read response: data byte(s) |
| last | CRC_RESP |
CRC-8 over the response bytes |
Broadcast commands (BROADCAST bit = 1, DEVICE_ADDR = 0x0) are write-only and produce no slave response.
The DATA_LENGTH field [5:4] of DEV_ADDR controls the number of data bytes in both write commands and read responses:
| DATA_LENGTH[5:4] | TPS929120-Q1 / TPS929160-Q1 | TPS929240-Q1 |
|---|---|---|
00 |
1 byte | 1 byte |
01 |
2 bytes | 4 bytes |
10 |
4 bytes | 16 bytes |
11 |
8 bytes | 24 bytes |
| Annotation | Description |
|---|---|
SYNC: OK (0x55) |
Valid synchronisation byte detected; start of a new frame |
DEV_ADDR: WRITE addr=0xX bcast=NO len=NB |
Device address byte decoded; R/W direction, device address (0–F), broadcast flag, and data length in bytes |
DEV_ADDR: READ addr=0xX bcast=NO len=NB |
As above for a read command (no data bytes follow from master) |
DEV_ADDR: WRITE addr=0x0 bcast=YES len=NB |
Broadcast write; no slave response will follow |
REG_ADDR: 0xXX |
Target register address |
DATA[n]: 0xXX |
Write data byte at zero-based index n |
CRC: PASS (calc=0xXX rx=0xXX) |
Command frame CRC-8 check passed |
CRC: FAIL (calc=0xXX rx=0xXX) |
Command frame CRC-8 check failed |
STATUS: 0xXX (flags) |
Write response byte; decoded flag names shown (FLAG_REF, FLAG_FS, FLAG_OUT, FLAG_PRETSD, FLAG_TSD, FLAG_POR, FLAG_ERR), or OK if all clear |
RESP[n]: 0xXX |
Read response data byte at zero-based index n |
CRC_RESP: PASS (calc=0xXX rx=0xXX) |
Response CRC-8 check passed |
CRC_RESP: FAIL (calc=0xXX rx=0xXX) |
Response CRC-8 check failed |
FlexWire uses an 8-bit CRC with polynomial X^8 + X^5 + X^4 + 1 and an initial value of 0xFF. Because UART transmits LSB first, the polynomial is reflected to 0x8C and processed with a right-shifting LFSR; the final remainder is then bit-reversed to produce the CRC byte. The CRC is computed over DEV_ADDR, REG_ADDR, and all DATA bytes; the SYNC byte is excluded. The same algorithm covers both the command CRC and the slave response CRC.
Unknown bytes: Bytes received while the state machine is in IDLE that are not 0x55 are silently discarded. This allows the HLA to resynchronise naturally after a gap or a CRC error without locking out decoding.
Framing errors: A framing error reported by the Async Serial analyzer resets the state machine to IDLE.
Command timeout: If more than 200µs elapses between UART frames while decoding a command (any state other than IDLE), the incomplete command is aborted and the state machine returns to IDLE.
The following example shows a read command capture decoded by the Flexwire HLA. The analyzer recognizes the correct SYNC, device address, register address with register name, and validates the CRC.
The FlexWire HLA will be slow when there is a large amount of data, as it is an HLA (not a Low Level Analyzer). After capturing data, right-click the screen to delete data outside the region of interest.
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