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Merge pull request #4777 from oharboe/cva6-upstream-rams
asap7/cva6: the RAMs as upstream has them, made macros
2 parents 3f8ab4e + afac85c commit 8d33f93

13 files changed

Lines changed: 705 additions & 112 deletions

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‎flow/designs/asap7/cva6/config.mk‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,8 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
@@ -64,27 +65,27 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
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$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
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$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
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$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
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$(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \
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$(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \
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$(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \
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$(PLATFORM_DIR)/verilog/fakeram7_64x25.sv
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$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include
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export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \
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$(PLATFORM_DIR)/lef/fakeram7_128x64.lef \
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$(PLATFORM_DIR)/lef/fakeram7_64x28.lef \
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$(PLATFORM_DIR)/lef/fakeram7_64x25.lef
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# The RAMs are upstream's, the RTL unmodified, and AUTO_MEMORIES makes
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# each a macro, cva6.memories naming its pins and byte enables: the
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# D-cache data (hpdcache_sram_wbyteenable_1rw) and directory
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# (hpdcache_sram_1rw), and the I-cache data and tag, which surgery.py
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# puts behind sram_cache's techno cut in place of pulp's tc_sram.
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export SYNTH_VERILOG_SURGERY = $(DESIGN_HOME)/$(PLATFORM)/cva6/surgery.py
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export AUTO_MEMORIES = 1
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export ADDITIONAL_MEMORIES = $(DESIGN_HOME)/$(PLATFORM)/cva6/cva6.memories
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \
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$(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \
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$(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \
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$(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib
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# Kepler LEC off for now: kepler-formal stops on the macros AUTO_MEMORIES
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# makes ("cva6_icache_data_sram cannot be found"). A new kepler-formal is
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# in the works; the Kepler team rewires LEC for cva6 with it.
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export LEC_CHECK = 0
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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‎flow/designs/asap7/cva6/cva6.memories‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,242 @@
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{
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"version": 1,
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"memories": [
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{
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"name": "cva6_icache_data_sram",
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"rows": 64,
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"bits": 256,
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"addr_w": 6,
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"rw_ports": 1,
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"mask_lanes": 32,
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"idiomatic": true,
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"reason": "the I-cache data RAM behind the techno cut (surgery.py): one read-write port, byte enables",
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"pins": [
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{
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"name": "clk",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "clk"
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},
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{
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"name": "cs",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "en"
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},
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{
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"name": "we",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "wmode"
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},
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{
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"name": "addr",
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"direction": "input",
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"width": 6,
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"port_id": "RW0",
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"function": "addr"
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},
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{
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"name": "wdata",
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"direction": "input",
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"width": 256,
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"port_id": "RW0",
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"function": "data_in"
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},
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{
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"name": "be",
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"direction": "input",
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"width": 32,
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"port_id": "RW0",
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"function": "mask"
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},
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{
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"name": "rdata",
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"direction": "output",
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"width": 256,
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"port_id": "RW0",
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"function": "data_out"
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}
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]
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},
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{
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"name": "cva6_icache_tag_sram",
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"rows": 64,
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"bits": 25,
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"addr_w": 6,
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"rw_ports": 1,
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"mask_lanes": 4,
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"mask_lane_width": 8,
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"idiomatic": true,
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"reason": "the I-cache tag RAM behind the techno cut (surgery.py): one read-write port, byte enables, the last 1 bit",
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"pins": [
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{
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"name": "clk",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "clk"
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},
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{
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"name": "cs",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "en"
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},
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{
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"name": "we",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "wmode"
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},
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{
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"name": "addr",
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"direction": "input",
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"width": 6,
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"port_id": "RW0",
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"function": "addr"
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},
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{
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"name": "wdata",
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"direction": "input",
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"width": 25,
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"port_id": "RW0",
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"function": "data_in"
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},
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{
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"name": "be",
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"direction": "input",
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"width": 4,
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"port_id": "RW0",
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"function": "mask"
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},
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{
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"name": "rdata",
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"direction": "output",
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"width": 25,
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"port_id": "RW0",
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"function": "data_out"
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}
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]
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},
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{
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"name": "hpdcache_sram_1rw",
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"rows": 64,
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"bits": 28,
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"addr_w": 6,
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"rw_ports": 1,
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"idiomatic": true,
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"reason": "the D-cache directory RAM: one read-write port",
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"pins": [
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{
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"name": "clk",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "clk"
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},
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{
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"name": "cs",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "en"
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},
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{
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"name": "we",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "wmode"
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},
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{
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"name": "addr",
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"direction": "input",
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"width": 6,
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"port_id": "RW0",
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"function": "addr"
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},
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{
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"name": "wdata",
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"direction": "input",
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"width": 28,
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"port_id": "RW0",
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"function": "data_in"
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},
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{
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"name": "rdata",
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"direction": "output",
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"width": 28,
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"port_id": "RW0",
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"function": "data_out"
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}
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]
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},
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{
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"name": "hpdcache_sram_wbyteenable_1rw",
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"rows": 128,
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"bits": 64,
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"addr_w": 7,
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"rw_ports": 1,
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"mask_lanes": 8,
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"idiomatic": true,
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"reason": "the D-cache data RAM, both ways of a set in a word: one read-write port, byte mask",
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"pins": [
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{
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"name": "clk",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "clk"
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},
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{
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"name": "cs",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "en"
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},
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{
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"name": "we",
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"direction": "input",
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"width": 1,
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"port_id": "RW0",
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"function": "wmode"
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},
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{
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"name": "addr",
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"direction": "input",
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"width": 7,
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"port_id": "RW0",
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"function": "addr"
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},
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{
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"name": "wdata",
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"direction": "input",
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"width": 64,
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"port_id": "RW0",
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"function": "data_in"
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},
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{
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"name": "wbyteenable",
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"direction": "input",
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"width": 8,
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"port_id": "RW0",
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"function": "mask"
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},
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{
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"name": "rdata",
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"direction": "output",
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"width": 64,
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"port_id": "RW0",
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"function": "data_out"
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}
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]
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}
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]
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}

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