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Description
I think I must be misreading the asap7 corner setup, because as far as I can tell the default flow evaluates setup timing at the fast / best-case corner — which would be backwards. I'd appreciate a sanity check before I conclude I've found a real problem.
What I see
flow/platforms/asap7/config.mk (upstream/master @ 7bf5a814e4) defaults the single timing corner to BC:
export CORNER ?= BC # line 197
export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES)and BC is the fast corner (0.77 V, 25 C, *_FF_* libs):
BC_VOLTAGE = 0.77 ; BC_TEMPERATURE = 25C
BC_NLDM_LIB_FILES_T = .../asap7sc7p5t_*_FF_nldm_*.lib.gz # FF = fast / best case
WC_NLDM_LIB_FILES_T = .../asap7sc7p5t_*_SS_nldm_*.lib.gz # SS = slow / worst case
TC_NLDM_LIB_FILES_T = .../asap7sc7p5t_*_TT_nldm_*.lib.gz # TT = typicalSince the flow is single-corner (LIB_FILES comes from the one selected CORNER), all STA — setup included — appears to run at FF by default. Setup is normally closed against the slow corner, so this looks wrong. gf180 has the same CORNER ?= BC; nangate45/sky130hd are single-typical-corner and look unaffected.
Minimal reproduction — gcd (smallest design, no corner override)
designs/asap7/gcd/config.mk sets no CORNER, so it inherits the platform default. Running it stock vs. forcing worst-case:
make DESIGN_CONFIG=./designs/asap7/gcd/config.mk # default (BC)
make DESIGN_CONFIG=./designs/asap7/gcd/config.mk CORNER=WC # worst-case| run | libraries actually loaded | worst setup slack |
|---|---|---|
default (BC) |
asap7sc7p5t_*_FF_nldm_* (fast) |
−35 ps |
CORNER=WC |
asap7sc7p5t_*_SS_nldm_* (slow) |
−347 ps |
(Slack values are worst slack reported at the same timing-driven global-placement stage,
identical clock and SDC; grep _FF_nldm/_SS_nldm in each run's log confirms which corner's
libraries were read.) The default run reads the fast libraries and reports ~−35 ps; the
same design at the worst-case corner is ~−347 ps — a ~10× difference, and the sign of the
engineering conclusion ("barely violating" vs "badly violating") flips with it.
So the stock gcd — and every asap7 design that doesn't override CORNER — is being timed at
the best-case corner, which under-reports setup violations by an order of magnitude here.
Questions
- Am I misreading this — is there a separate setup/hold corner mechanism I'm missing that makes setup actually use SS despite
CORNER ?= BC? - If not: is
BCan intentional asap7/gf180 choice (e.g. tied to how these predictive PDKs were characterized), or an oversight? If intentional, could it be documented, since "asap7 setup is reported at best-case" strongly affects how the numbers should be read?
Happy to send a PR (flip the default to WC/TC, or add docs) once I know which it is.
Activity
oharboe commentedon Nov 1, 2026
Interesting question, I asked Claude to do some digging.
1. Is there a separate setup/hold corner? No. With
CORNER ?= BC, every asap7 stage, setup included, is timed with the FF libraries. gf180 has the same default.2. Intentional or an oversight? Nothing records why. asap7 started on a single TT library (4eeefb6, Jan 2021).
CORNER ?= BCarrived in a platform update with no stated rationale (67b9571, Mar 2021). That was six months before ORFS could load more than one corner (CORNERS, f9463be, Sep 2021), so one corner was all the flow could do at the time. gf180 copied the pattern at bring-up (5c761de). A 2023 attempt to tieCORNERSto asap7'sCORNERnaming (#837) was reverted the next day (#839).Flipping the ORFS default is a lot of work, and users have no reason to keep it.
CORNER ?= BCis also the default for the regression suite, and every asap7 clock period andrules.jsonhas been calibrated against FF since 2021. A different corner changes the results of every asap7 design at once. That amounts to fuzzing the inputs, and designs that sit near an edge will turn up problems that have nothing to do with the corner.#4681 shows what that looks like. Switching asap7/aes-block to slang made the parent's netlist slightly smaller, while the macros stayed the same.
CORE_UTILIZATION 47then gave a slightly smaller core (11,857 vs 11,875 µm²), the macros (9,792 µm² with halos) crossed the ~82% of the core where macro placement fails with MPL-0003, and the build stopped. read_verilog fails at the same core, and the nearest failing and passing cores differ by one site column. A corner flip would do this to every asap7 design at once: each failure investigated, each fixed or re-floorplanned, and eachrules.jsonre-baselined.A user's own design isn't bound by any of that, and there is no reason to prefer FF. Set
CORNER=WCfor setup, orCORNERS(below) for setup and hold together.Single corner is the default, not a limit. LibreLane (the OpenLane 2 successor) does multi-corner analysis through
STA_CORNERSandDEFAULT_CORNER, picks corners per step withRSZ_CORNERS,CTS_CORNERSandPNR_CORNERS, and extracts SPEF per corner. ORFS has the mechanism too: withCORNERSset,read_liberty.tclloads every corner into one OpenROAD session, so repair and the reports see all of them. ihp-sg13g2'si2c-gpio-expanderuses it (CORNERS = slow fast).On asap7 it needs these changes:
<CORNER>_<LIB_MODEL>_LIB_FILES, whileread_liberty.tcllooks up<CORNER>_LIB_FILES.CORNERS="WC BC"finds nothing.ADDITIONAL_LIBS: macro and multi-bit flop libraries are folded intoLIB_FILES, which multi-corner mode ignores, so macros lose their timing. They need reading into every corner, asAUTO_MEMORIESalready does.LIB_FILESand stays single-corner. SetCORNER=WCfor synthesis.setRC.tclsets one RC corner for all liberty corners. Separate RC corners would needset_layer_rc -corner.CORNERSread per stage. In bazel-orfs,stage_argumentscan already set it per stage.#4771 (consistent
<COMMAND>_ARGS) doesn't need to change for this. LibreLane's per-step corners (RSZ_CORNERS,CTS_CORNERS,PNR_CORNERS) choose which liberty and RC data a step loads.repair_timingandclock_tree_synthesisthen work on whatever is loaded and take no corner option. That makes corners variables that name files, which #4771 leaves to variables of their own, so a build can declare them as a stage's inputs. Corner-specific repair is item 5:CORNERSwith a different value per stage.A test in bazel-orfs could carry 1 and 2 as a patch on ORFS and build asap7
gcdthree ways:CORNER=BC(today's default),CORNER=WC, andCORNERS="WC BC"withCORNER=WCfor synthesis. Pass/fail checks would be:report_checks -cornerreports setup at WC and hold at BC;With setup and hold WNS for each arm, that test would show what flipping the default, or running both corners, costs.
maliberty commentedon Nov 4, 2026
It looks like an arbitrary choice in the mist of time when we only had single corner analysis. As a tool to drive OR development it hardly matters which corner we use. We could now setup a two corner analysis. I don't recall the history of CORNERS and what broke but we could try again.
mguthaus commentedon Nov 4, 2026
I agree it doesn't matter much as test cases, but academics are using this for evaluation of research ideas, so it should probably be fixed to prevent incorrect claims.
Transitioning to multi corner is definitely a good suggestion and is probably needed for both of the above cases. It probably coincides with needed work in the resizer etc.
What about continuity of the regression tests? These will likely break if it goes to multi corner as well.
oharboe commentedon Nov 4, 2026
There's been some thinking about how to measure QoR. It all started with the observation that percent of WNS is very misleading because WNS is by design small and then it snowballed into #4583
Multicorner would make QoR evaluation across designs even more interesting.
maliberty commentedon Nov 4, 2026
We can update our limits but it has the possibility to create more confusion for academics trying to compare results across such a switch.
mguthaus commentedon Nov 4, 2026
Perfect is the enemy of good. If they do that, then it is just ineptitude and we can't prevent that. Most academics aren't comparing an old version of OR/ORFS with a new version, but a version that they have modified with the baseline before they modified it.
oharboe commentedon Nov 4, 2026
Since ORFS is a regression testing suite, surely there are better designs/benchmarks to use for academic study.
I wouldn't use unit-tests to measure the performance of a CPU, I'd use CoreMark, SPEC, etc.
Isn't there something like that for EDA tools?
mguthaus commentedon Nov 4, 2026
Unfortunately, many papers are using these benchmarks.
oharboe commentedon Nov 4, 2026
Hmm.... so all the more reasons to include something that resembles benchmarks in ORFS designs then. I've got CoralNPU + XiangShan in the pipeline. I think I saw some EDA competition designs, but I can't find them now. Do you happen to know some good ones?
mguthaus commentedon Nov 4, 2026
I've already got CoralNPU in HighTide. XiangShan would be a good addition.
mguthaus commentedon Nov 4, 2026
EDA competitions are tending to use the ORFS designs too....
oharboe commentedon Nov 4, 2026
😌
You may be interested in this new setup, it has wired up new features in OpenROAD, particularly generate_ram to do register files + verilog surgery. It needs a few more PRs merged before I can flip it to ready to review.
#4653
You can follow the work in bazel-orfs, I haven't thrown it the towel yet.
maliberty commentedon Nov 5, 2026
Don't they compare against a previously published result?
mguthaus commentedon Nov 5, 2026
Sometimes. I've seen some comparing with baseline ORFS.
In any case, it seems like multi corner tests should be a thing...
raphaelrowley commentedon Nov 6, 2026
I am interested in this conversation, what is the conclusion?
Perhaps a separate issue but
These two values should be swapped