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FakeRAM2.0: apply the ORFS asap7 backend to the vendored copy #4603
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| # ORFS ASAP7 package |
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| @@ -0,0 +1,88 @@ | ||
| import json | ||
| import sys | ||
| from pathlib import Path | ||
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| from utils.class_process import Process | ||
| from utils.memory_config import MemoryConfig | ||
| from utils.memory_factory import MemoryFactory | ||
| from utils.timing_data import TimingData | ||
| from utils.ram_liberty_exporter import RAMLibertyExporter | ||
| from utils.lef_exporter import LefExporter | ||
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| ASAP7_PROCESS_CONFIG = { | ||
| "tech_nm": 7, | ||
| "voltage": 0.7, | ||
| "metal_prefix": "M", | ||
| "metal_layer": "M4", | ||
| "pin_width_nm": 24, | ||
| "pin_pitch_nm": 48, | ||
| "metal_track_pitch_nm": 48, | ||
| "manufacturing_grid_nm": 1, | ||
| "contacted_poly_pitch_nm": 54, | ||
| "fin_pitch_nm": 27, | ||
| "column_mux_factor": 1, | ||
| "snap_width_nm": 190, | ||
| "snap_height_nm": 1400, | ||
| } | ||
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| ASAP7_TIMING_CONFIG = { | ||
| "cycle_time": 1.0, | ||
| "access_time": 0.5, | ||
| "setup_time": 0.1, | ||
| "hold_time": 0.05, | ||
| "leakage": 0.001, | ||
| } | ||
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| def run_orfs_asap7(platform: str, out_dir: Path, json_path: Path): | ||
| if platform != "asap7": | ||
| sys.stderr.write(f"FakeRAM2.0 orfs_asap7: unsupported platform {platform}\n") | ||
| return 1 | ||
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| try: | ||
| data = json.loads(json_path.read_text()) | ||
| memories = data.get("memories", []) | ||
| except Exception as e: | ||
| sys.stderr.write(f"FakeRAM2.0 orfs_asap7: failed to read {json_path}: {e}\n") | ||
| return 1 | ||
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| out_dir.mkdir(parents=True, exist_ok=True) | ||
| converted = sorted( | ||
| (m for m in memories if m.get("idiomatic")), key=lambda m: m["name"] | ||
| ) | ||
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| process = Process(ASAP7_PROCESS_CONFIG) | ||
| timing_data = TimingData(ASAP7_TIMING_CONFIG) | ||
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| for m in converted: | ||
| name = m["name"] | ||
| bits = m.get("bits", 32) | ||
| rows = m.get("rows", 128) | ||
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| sram_dict = { | ||
| "name": name, | ||
| "width": bits, | ||
| "depth": rows, | ||
| "banks": 1, | ||
| } | ||
| mem_config = MemoryConfig.from_json(sram_dict) | ||
| ram = MemoryFactory.create(mem_config, "RAM", "SP", process, timing_data) | ||
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| # Export Liberty | ||
| lib_path = out_dir / f"{name}.lib" | ||
| with open(lib_path, "w") as f: | ||
| RAMLibertyExporter(ram).export(f) | ||
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| pre_lib_path = out_dir / f"{name}_pre_layout.lib" | ||
| with open(pre_lib_path, "w") as f: | ||
| RAMLibertyExporter(ram).export(f) | ||
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| # Export LEF | ||
| lef_path = out_dir / f"{name}.lef" | ||
| with open(lef_path, "w") as f: | ||
| LefExporter(ram).export(f) | ||
|
oharboe marked this conversation as resolved.
Resolved
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| (out_dir / "blackboxes.txt").write_text( | ||
| "".join(f"{m['name']}\n" for m in converted) | ||
| ) | ||
| return 0 | ||
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@@ -119,6 +119,11 @@ def get_macro_dimensions(self, width_in_bits, depth, num_banks, additional_heigh | |
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| total_height += additional_height | ||
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| min_height = max( | ||
| 3.5, self.snap_height_nm / 1000.0 if self.snap_height_nm else 0 | ||
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Member
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Where did 3.5 come from?
Collaborator
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Good question. I can't find a source. It came in as a bare literal in the original AUTO_MEMORIES patch (a632406, I don't see a PDN reason for a height floor. The macro's M4 power rails are horizontal and the M5 straps are vertical, so strap coverage depends on the macro's width, not its height. That's the floor that will follow (#4597), derived from the 5.4 µm M5 pitch in I'd rather keep this PR a verbatim move and decide in a follow-up whether to drop the 3.5 floor or move it into
Member
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Fine but please do follow up
Collaborator
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Follow-up: #4608. Nothing in the history explained the 3.5, so the first commit drops it and a forced 4×25 memory fails with "not enough tracks". The second commit sizes the height from the pin count instead: Other cleanup that came up in the sweep:
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| ) | ||
| total_height = max(total_height, min_height) | ||
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| return (total_width, total_height) | ||
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| def get_tech_nm(self): | ||
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