diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
index 5e47afd713..31a0ed36c6 100644
--- a/docs/user/FlowVariables.md
+++ b/docs/user/FlowVariables.md
@@ -225,6 +225,7 @@ configuration file.
 | <a name="POST_SYNTH_TCL"></a>POST_SYNTH_TCL| Specifies a Tcl script with commands to run after synthesis ODB generation.| |
 | <a name="POST_TAPCELL_TCL"></a>POST_TAPCELL_TCL| Specifies a Tcl script with commands to run after tapcell.| |
 | <a name="POS_CLKGATE_AND_PORTS"></a>POS_CLKGATE_AND_PORTS| Specifies the active high enable clock gating cell and port names when used in conjunction with the INFER_CLKGATES variable. Format is "cell_name enable_port:master_clock:gated_clock"| |
+| <a name="POWER_FILE_SCOPE"></a>POWER_FILE_SCOPE| The SAIF or VCD scope of the current design. Typically the test bench name and design under the test instance name. Scope levels are separated with '/'.| |
 | <a name="PRE_CTS_TCL"></a>PRE_CTS_TCL| Specifies a Tcl script with commands to run before CTS.| |
 | <a name="PRE_DENSITY_FILL_TCL"></a>PRE_DENSITY_FILL_TCL| Specifies a Tcl script with commands to run before density fill.| |
 | <a name="PRE_DETAIL_PLACE_TCL"></a>PRE_DETAIL_PLACE_TCL| Specifies a Tcl script with commands to run before detailed placement.| |
@@ -272,6 +273,7 @@ configuration file.
 | <a name="RTLMP_WIRELENGTH_WT"></a>RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0|
 | <a name="RUN_LOG_NAME_STEM"></a>RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run|
 | <a name="RUN_SCRIPT"></a>RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| |
+| <a name="SAIF_FILE"></a>SAIF_FILE| Specifies the Switching Activity Interchange Format (SAIF) file containing pin activities and duty cycles for use in power calculation.| |
 | <a name="SC_LEF"></a>SC_LEF| Path to technology standard cell LEF file.| |
 | <a name="SDC_FILE"></a>SDC_FILE| The path to design constraint (SDC) file.| |
 | <a name="SEAL_GDS"></a>SEAL_GDS| Seal macro to place around the design.| |
@@ -331,6 +333,7 @@ configuration file.
 | <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
 | <a name="UNSET_ABC9_BOX_CELLS"></a>UNSET_ABC9_BOX_CELLS| List of cells to unset the abc9_box attribute on| |
 | <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
+| <a name="VCD_FILE"></a>VCD_FILE| Specifies the Value Change Dump (VCD) file containing pin activities and duty cycles for use in power calculation.| |
 | <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
 | <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| |
 | <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| |
@@ -679,6 +682,7 @@ configuration file.
 - [MIN_CLK_ROUTING_LAYER](#MIN_CLK_ROUTING_LAYER)
 - [PLATFORM](#PLATFORM)
 - [PLATFORM_TCL](#PLATFORM_TCL)
+- [POWER_FILE_SCOPE](#POWER_FILE_SCOPE)
 - [PROCESS](#PROCESS)
 - [RCX_RULES](#RCX_RULES)
 - [RECOVER_POWER](#RECOVER_POWER)
@@ -686,11 +690,13 @@ configuration file.
 - [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER)
 - [RUN_LOG_NAME_STEM](#RUN_LOG_NAME_STEM)
 - [RUN_SCRIPT](#RUN_SCRIPT)
+- [SAIF_FILE](#SAIF_FILE)
 - [SC_LEF](#SC_LEF)
 - [SEAL_GDS](#SEAL_GDS)
 - [SLEW_MARGIN](#SLEW_MARGIN)
 - [TAP_CELL_NAME](#TAP_CELL_NAME)
 - [TECH_LEF](#TECH_LEF)
 - [USE_FILL](#USE_FILL)
+- [VCD_FILE](#VCD_FILE)
 - [WIRE_LOAD_MODEL](#WIRE_LOAD_MODEL)
 
diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl
index 5accb72a34..ed6f2ec6ef 100644
--- a/flow/scripts/report_metrics.tcl
+++ b/flow/scripts/report_metrics.tcl
@@ -6,6 +6,30 @@ proc report_puts { out } {
   close $fileId
 }
 
+#-----------------------------------------------------------------------------
+# Gets the power file scope arg and escapes, if necessary
+#-----------------------------------------------------------------------------
+proc get_power_file_scope_args { } {
+  set args [list]
+
+  if { [env_var_exists_and_non_empty POWER_FILE_SCOPE] } {
+    set scope_val $::env(POWER_FILE_SCOPE)
+
+    # 1. Strip surrounding quotes from shell/Make
+    set scope_val [string trim $scope_val "\"'"]
+
+    # 2. Normalize: remove ALL backslashes preceding [, ], or .
+    regsub -all {\\+(\[|\]|\.)} $scope_val {\1} scope_val
+
+    # 3. Apply exactly one backslash escape to [, ], and .
+    regsub -all {(\[|\]|\.)} $scope_val {\\\1} scope_val
+
+    lappend args -scope $scope_val
+  }
+
+  return $args
+}
+
 proc report_metrics { stage when { include_erc true } { include_clock_skew true } } {
   if { $::env(SKIP_REPORT_METRICS) } {
     return
@@ -234,6 +258,15 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true
   report_puts "\n=========================================================================="
   report_puts "$when report_power"
   report_puts "--------------------------------------------------------------------------"
+
+  set scope_args [get_power_file_scope_args]
+  if { [env_var_exists_and_non_empty SAIF_FILE] } {
+    read_saif {*}$scope_args $::env(SAIF_FILE)
+    report_activity_annotation
+  } elseif { [env_var_exists_and_non_empty VCD_FILE] } {
+    read_vcd {*}$scope_args $::env(VCD_FILE)
+    report_activity_annotation
+  }
   if { [env_var_exists_and_non_empty CORNERS] } {
     foreach corner $::env(CORNERS) {
       report_puts "Corner: $corner"
diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json
index f5c5c00c26..a98b321bf1 100644
--- a/flow/scripts/variables.json
+++ b/flow/scripts/variables.json
@@ -831,6 +831,10 @@
       "synth"
     ]
   },
+  "POWER_FILE_SCOPE": {
+    "description": "The SAIF or VCD scope of the current design. Typically the test bench name and design under the test instance name. Scope levels are separated with '/'.\n",
+    "type": "string"
+  },
   "PRE_CTS_TCL": {
     "description": "Specifies a Tcl script with commands to run before CTS.\n",
     "stages": [
@@ -1124,6 +1128,10 @@
   "RUN_SCRIPT": {
     "description": "Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.\n"
   },
+  "SAIF_FILE": {
+    "description": "Specifies the Switching Activity Interchange Format (SAIF) file containing pin activities and duty cycles for use in power calculation.\n",
+    "type": "string"
+  },
   "SC_LEF": {
     "description": "Path to technology standard cell LEF file.\n"
   },
@@ -1527,6 +1535,10 @@
     "default": 0,
     "description": "Whether to perform metal density filling.\n"
   },
+  "VCD_FILE": {
+    "description": "Specifies the Value Change Dump (VCD) file containing pin activities and duty cycles for use in power calculation.\n",
+    "type": "string"
+  },
   "VERILOG_DEFINES": {
     "description": "Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`\n",
     "stages": [
diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml
index d0634da90d..9fc66a920a 100644
--- a/flow/scripts/variables.yaml
+++ b/flow/scripts/variables.yaml
@@ -1741,3 +1741,18 @@ GRT_SEED:
     - grt
   tunable: 1
   type: int
+SAIF_FILE:
+  description: >
+    Specifies the Switching Activity Interchange Format (SAIF) file containing pin
+    activities and duty cycles for use in power calculation.
+  type: string
+POWER_FILE_SCOPE:
+  description: >
+    The SAIF or VCD scope of the current design. Typically the test bench name and
+    design under the test instance name. Scope levels are separated with '/'.
+  type: string
+VCD_FILE:
+  description: >
+    Specifies the Value Change Dump (VCD) file containing pin activities and duty
+    cycles for use in power calculation.
+  type: string