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asap7/cva6: the RAMs as upstream has them, made macros #4777
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maliberty
merged 4 commits into
The-OpenROAD-Project:master
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oharboe:cva6-upstream-rams
Nov 6, 2026
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5494310
asap7/cva6: the D-cache RAMs as upstream has them, made macros
oharboe 948c46b
asap7/cva6: the I-cache RAMs behind the techno cut, made macros
oharboe 5b73a13
cva6: say what differs from upstream
oharboe afac85c
asap7/cva6: Kepler LEC check off for now
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,242 @@ | ||
| { | ||
| "version": 1, | ||
| "memories": [ | ||
| { | ||
| "name": "cva6_icache_data_sram", | ||
| "rows": 64, | ||
| "bits": 256, | ||
| "addr_w": 6, | ||
| "rw_ports": 1, | ||
| "mask_lanes": 32, | ||
| "idiomatic": true, | ||
| "reason": "the I-cache data RAM behind the techno cut (surgery.py): one read-write port, byte enables", | ||
| "pins": [ | ||
| { | ||
| "name": "clk", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "clk" | ||
| }, | ||
| { | ||
| "name": "cs", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "en" | ||
| }, | ||
| { | ||
| "name": "we", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "wmode" | ||
| }, | ||
| { | ||
| "name": "addr", | ||
| "direction": "input", | ||
| "width": 6, | ||
| "port_id": "RW0", | ||
| "function": "addr" | ||
| }, | ||
| { | ||
| "name": "wdata", | ||
| "direction": "input", | ||
| "width": 256, | ||
| "port_id": "RW0", | ||
| "function": "data_in" | ||
| }, | ||
| { | ||
| "name": "be", | ||
| "direction": "input", | ||
| "width": 32, | ||
| "port_id": "RW0", | ||
| "function": "mask" | ||
| }, | ||
| { | ||
| "name": "rdata", | ||
| "direction": "output", | ||
| "width": 256, | ||
| "port_id": "RW0", | ||
| "function": "data_out" | ||
| } | ||
| ] | ||
| }, | ||
| { | ||
| "name": "cva6_icache_tag_sram", | ||
| "rows": 64, | ||
| "bits": 25, | ||
| "addr_w": 6, | ||
| "rw_ports": 1, | ||
| "mask_lanes": 4, | ||
| "mask_lane_width": 8, | ||
| "idiomatic": true, | ||
| "reason": "the I-cache tag RAM behind the techno cut (surgery.py): one read-write port, byte enables, the last 1 bit", | ||
| "pins": [ | ||
| { | ||
| "name": "clk", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "clk" | ||
| }, | ||
| { | ||
| "name": "cs", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "en" | ||
| }, | ||
| { | ||
| "name": "we", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "wmode" | ||
| }, | ||
| { | ||
| "name": "addr", | ||
| "direction": "input", | ||
| "width": 6, | ||
| "port_id": "RW0", | ||
| "function": "addr" | ||
| }, | ||
| { | ||
| "name": "wdata", | ||
| "direction": "input", | ||
| "width": 25, | ||
| "port_id": "RW0", | ||
| "function": "data_in" | ||
| }, | ||
| { | ||
| "name": "be", | ||
| "direction": "input", | ||
| "width": 4, | ||
| "port_id": "RW0", | ||
| "function": "mask" | ||
| }, | ||
| { | ||
| "name": "rdata", | ||
| "direction": "output", | ||
| "width": 25, | ||
| "port_id": "RW0", | ||
| "function": "data_out" | ||
| } | ||
| ] | ||
| }, | ||
| { | ||
| "name": "hpdcache_sram_1rw", | ||
| "rows": 64, | ||
| "bits": 28, | ||
| "addr_w": 6, | ||
| "rw_ports": 1, | ||
| "idiomatic": true, | ||
| "reason": "the D-cache directory RAM: one read-write port", | ||
| "pins": [ | ||
| { | ||
| "name": "clk", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "clk" | ||
| }, | ||
| { | ||
| "name": "cs", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "en" | ||
| }, | ||
| { | ||
| "name": "we", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "wmode" | ||
| }, | ||
| { | ||
| "name": "addr", | ||
| "direction": "input", | ||
| "width": 6, | ||
| "port_id": "RW0", | ||
| "function": "addr" | ||
| }, | ||
| { | ||
| "name": "wdata", | ||
| "direction": "input", | ||
| "width": 28, | ||
| "port_id": "RW0", | ||
| "function": "data_in" | ||
| }, | ||
| { | ||
| "name": "rdata", | ||
| "direction": "output", | ||
| "width": 28, | ||
| "port_id": "RW0", | ||
| "function": "data_out" | ||
| } | ||
| ] | ||
| }, | ||
| { | ||
| "name": "hpdcache_sram_wbyteenable_1rw", | ||
| "rows": 128, | ||
| "bits": 64, | ||
| "addr_w": 7, | ||
| "rw_ports": 1, | ||
| "mask_lanes": 8, | ||
| "idiomatic": true, | ||
| "reason": "the D-cache data RAM, both ways of a set in a word: one read-write port, byte mask", | ||
| "pins": [ | ||
| { | ||
| "name": "clk", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "clk" | ||
| }, | ||
| { | ||
| "name": "cs", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "en" | ||
| }, | ||
| { | ||
| "name": "we", | ||
| "direction": "input", | ||
| "width": 1, | ||
| "port_id": "RW0", | ||
| "function": "wmode" | ||
| }, | ||
| { | ||
| "name": "addr", | ||
| "direction": "input", | ||
| "width": 7, | ||
| "port_id": "RW0", | ||
| "function": "addr" | ||
| }, | ||
| { | ||
| "name": "wdata", | ||
| "direction": "input", | ||
| "width": 64, | ||
| "port_id": "RW0", | ||
| "function": "data_in" | ||
| }, | ||
| { | ||
| "name": "wbyteenable", | ||
| "direction": "input", | ||
| "width": 8, | ||
| "port_id": "RW0", | ||
| "function": "mask" | ||
| }, | ||
| { | ||
| "name": "rdata", | ||
| "direction": "output", | ||
| "width": 64, | ||
| "port_id": "RW0", | ||
| "function": "data_out" | ||
| } | ||
| ] | ||
| } | ||
| ] | ||
| } |
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@nanocoh I'm disabling this for now. Once kepler-formal is bumped in bazel bcr and #4732 is merged, we're in a great position to wire up cva6 properly to cva6.
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ok. lets do that.
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Some update. The issue was not with the tool but with missing memory files that were added with this change and need to be given to the formal check. Added the fix to #4329