From 92833249ee88a3381523ede3f8573db798e3c32a Mon Sep 17 00:00:00 2001 From: Bandham Balaji Date: Fri, 6 Nov 2026 21:51:21 +0530 Subject: [PATCH] asap7: fix V5.M6.AUX.2 and V7.M8.AUX.2 edge orientation in KLayout DRC In asap7_tech_1x_201209.lef, Metal 6 and Metal 8 are horizontal routing layers. In flow/platforms/asap7/drc/asap7.lydrc, rules V5.M6.AUX.2 and V7.M8.AUX.2 check that via width matches metal width along the direction perpendicular to metal length using .edges.with_angle(90). Because M6 and M8 are horizontal, selecting 90-degree edges checks vertical edges along the length of the metal instead of across its width. This falsely flags legal standard vias (e.g. VIA56 and VIA78) and wide power strap vias as DRC violations. Fix both rules by selecting horizontal edges with .edges.with_angle(0), matching the M4 check on rule V3.M4.AUX.2. Fixes #4738. Signed-off-by: Bandham Balaji --- flow/platforms/asap7/drc/asap7.lydrc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flow/platforms/asap7/drc/asap7.lydrc b/flow/platforms/asap7/drc/asap7.lydrc index 47bf0b8a7a..8ad03de835 100644 --- a/flow/platforms/asap7/drc/asap7.lydrc +++ b/flow/platforms/asap7/drc/asap7.lydrc @@ -428,7 +428,7 @@ v5.width(24.nm).output("V5.W.1", "V5.W.1 : Min. width of V5 : 24nm") v5.space(33.nm, euclidian).output("V5.S.1-2-3", "V5.S.1-2-3 : Min. spacing between V5 : 33nm") v5.interacting(m5.enclosing(v5, 11.nm, projection, two_connected_sides_allowed).edges - m5.enclosing(v5, 11.nm, projection, one_side_allowed).edges).output("V5.M5.EN.1", "V5.M5.EN.1 : Min. enclosure of V5 by M5 on at least two opposite sides : 11nm") ((v5 - m5) + (v5 - m6)).output("V5.AUX.1" "V5.AUX.1 : V5 must be inside M5 and M6") -v5.not_interacting(m6.enclosing(v5, 1.dbu, projection, two_opposite_sides_allowed).edges.with_angle(90)).output("V5.M6.AUX.2", "V5.M6.AUX.2 : V5 must exactly be the same width as M6 along the direction perpendicular to the M6 length") +v5.not_interacting(m6.enclosing(v5, 1.dbu, projection, two_opposite_sides_allowed).edges.with_angle(0)).output("V5.M6.AUX.2", "V5.M6.AUX.2 : V5 must exactly be the same width as M6 along the direction perpendicular to the M6 length") ### M6 @@ -482,7 +482,7 @@ v7.width(32.nm).output("V7.W.1", "V7.W.1 : Min. width of V7 : 32nm") v7.space(45.nm, euclidian).output("V7.S.1-2-3", "V7.S.1-2-3 : Min. spacing between V7 : 45nm") v7.interacting(m7.enclosing(v7, 11.nm, projection, two_connected_sides_allowed).edges - m7.enclosing(v7, 11.nm, projection, one_side_allowed).edges).output("V7.M7.EN.1", "V7.M7.EN.1 : Min. enclosure of V7 by M7 on at least two opposite sides : 11nm") ((v7 - m7) + (v7 - m8)).output("V7.AUX.1" "V7.AUX.1 : V7 must be inside M7 and M8") -v7.not_interacting(m8.enclosing(v7, 1.dbu, projection, two_opposite_sides_allowed).edges.with_angle(90)).output("V7.M8.AUX.2", "V7.M8.AUX.2 : V7 must exactly be the same width as M8 along the direction perpendicular to the M8 length") +v7.not_interacting(m8.enclosing(v7, 1.dbu, projection, two_opposite_sides_allowed).edges.with_angle(0)).output("V7.M8.AUX.2", "V7.M8.AUX.2 : V7 must exactly be the same width as M8 along the direction perpendicular to the M8 length") ### M8