synth: never map logic onto a hardened block; update OpenROAD

docs/user/FlowVariables.md

@@ -356,6 +356,7 @@ configuration file.
 - [ADDITIONAL_MEMORIES](#ADDITIONAL_MEMORIES)
 - [AUTO_MEMORIES_MACRO_PLACE](#AUTO_MEMORIES_MACRO_PLACE)
 - [AUTO_MEMORIES_REGFILES](#AUTO_MEMORIES_REGFILES)
+- [BLOCKS](#BLOCKS)
 - [CACHED_REPORTS](#CACHED_REPORTS)
 - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE)
 - [DFF_LIB_FILE](#DFF_LIB_FILE)
@@ -669,7 +670,6 @@ configuration file.
 - [ADDITIONAL_LEFS](#ADDITIONAL_LEFS)
 - [ADDITIONAL_LIBS](#ADDITIONAL_LIBS)
 - [AUTO_MEMORIES](#AUTO_MEMORIES)
-- [BLOCKS](#BLOCKS)
 - [CAP_MARGIN](#CAP_MARGIN)
 - [CDL_FILES](#CDL_FILES)
 - [CORNER](#CORNER)

flow/scripts/synth_preamble.tcl

@@ -302,6 +302,13 @@ if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
     lappend lib_dont_use_args -dont_use $cell
   }
 }
+# Never map logic onto a hardened block. A block's timing model gives a
+# constant output a function, and ABC would take the block for a gate.
+if { [env_var_exists_and_non_empty BLOCKS] } {
+  foreach block $::env(BLOCKS) {
+    lappend lib_dont_use_args -dont_use $block
+  }
+}
 
 # Technology mapping for cells
 set abc_args [list -script $abc_script \

flow/scripts/variables.yaml

@@ -1134,6 +1134,8 @@ BLOCKS:
   description: >
     Blocks used as hard macros in a hierarchical flow. Do note that you have to
     specify block-specific inputs file in the directory mentioned by Makefile.
+  stages:
+    - synth
 CDL_FILES:
   description: |
     Insert additional Circuit Description Language (`.cdl`) netlist files.