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synth_syn: read the platform's clock gate as the Yosys flow does - #4802

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oharboe:synth-syn-clkgate
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oharboe:synth-syn-clkgate

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@oharboe oharboe commented Nov 7, 2026

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Before: OpenROAD's own synthesis (SYNTH_USE_SYN=1, synth_syn.tcl) did not read the platform's clock gate, so asap7/swerv_wrapper, which instantiates OPENROAD_CLKGATE, listed $(CLKGATE_MAP_FILE) among its VERILOG_FILES.
Now: synth_syn.tcl adds CLKGATE_MAP_FILE when it is set, as the Yosys flow does in synth_preamble.tcl, and swerv_wrapper lists only its own sources.

Under make the same file is read, once. A flow that reads a design's config.mk without the platform's variables can no longer leave $(CLKGATE_MAP_FILE) unresolved in VERILOG_FILES; that was the failure seen, unknown module 'OPENROAD_CLKGATE'.

Tested: asap7/swerv_wrapper synthesis with SYNTH_USE_SYN=1 through bazel-orfs, which has carried this change since October.

🤖 Generated with Claude Code

The Yosys flow adds CLKGATE_MAP_FILE to the frontend's inputs itself
(synth_preamble.tcl, for both the slang and the Yosys Verilog
frontends). OpenROAD's own synthesis (SYNTH_USE_SYN, synth_syn.tcl) did
not, so asap7/swerv_wrapper, which instantiates OPENROAD_CLKGATE and
synthesises with SYNTH_USE_SYN, listed $(CLKGATE_MAP_FILE) in its
VERILOG_FILES: a platform file in a design's source list, and one that
a flow reading config.mk without the platform's variables cannot
resolve ("unknown module 'OPENROAD_CLKGATE'").

synth_syn.tcl now adds CLKGATE_MAP_FILE when it is set, and
swerv_wrapper no longer names it. Under make the file read is the same
one, read once.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

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Code Review

This pull request removes the CLKGATE_MAP_FILE from the VERILOG_FILES list in the swerv_wrapper configuration for the asap7 design. Instead, the clock gate map file is conditionally appended to the elaboration arguments in synth_syn.tcl if the CLKGATE_MAP_FILE environment variable exists and is not empty. I have no feedback to provide as there are no review comments.

@oharboe
oharboe marked this pull request as ready for review November 7, 2026 19:51
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🔍 QoR check

Metrics reflect the PR merge build — i.e. what will land on the target branch.

Commit 0954560 · Jenkins build #1 · Baseline: build · View build on dashboard

62 design(s) checked — 0 with regression(s), 0 without a comparable baseline.

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2 participants