From 5ccba7772cbbe0af59a2a5009eef98a16d33b9fc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Sat, 7 Nov 2026 19:37:10 +0100
Subject: [PATCH] synth_syn: read the platform's clock gate as the Yosys flow
 does
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The Yosys flow adds CLKGATE_MAP_FILE to the frontend's inputs itself
(synth_preamble.tcl, for both the slang and the Yosys Verilog
frontends). OpenROAD's own synthesis (SYNTH_USE_SYN, synth_syn.tcl) did
not, so asap7/swerv_wrapper, which instantiates OPENROAD_CLKGATE and
synthesises with SYNTH_USE_SYN, listed $(CLKGATE_MAP_FILE) in its
VERILOG_FILES: a platform file in a design's source list, and one that
a flow reading config.mk without the platform's variables cannot
resolve ("unknown module 'OPENROAD_CLKGATE'").

synth_syn.tcl now adds CLKGATE_MAP_FILE when it is set, and
swerv_wrapper no longer names it. Under make the file read is the same
one, read once.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
---
 flow/designs/asap7/swerv_wrapper/config.mk | 3 +--
 flow/scripts/synth_syn.tcl                 | 6 ++++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk
index 055969887d..4692da5f2e 100644
--- a/flow/designs/asap7/swerv_wrapper/config.mk
+++ b/flow/designs/asap7/swerv_wrapper/config.mk
@@ -45,8 +45,7 @@ export SYNTH_KEEP_MODULES ?= \
 export LIB_MODEL = CCS
 
 export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
-                       $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v \
-                       $(CLKGATE_MAP_FILE)
+                       $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc
 
 export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef))
diff --git a/flow/scripts/synth_syn.tcl b/flow/scripts/synth_syn.tcl
index 52617bd5ae..eb6ce193cf 100644
--- a/flow/scripts/synth_syn.tcl
+++ b/flow/scripts/synth_syn.tcl
@@ -33,6 +33,12 @@ set elaborate_args [list \
 set verilog_files [synth_verilog_files]
 lappend elaborate_args {*}$verilog_files
 
+# The platform's clock gate, as the Yosys flow reads it
+# (synth_preamble.tcl)
+if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } {
+  lappend elaborate_args $::env(CLKGATE_MAP_FILE)
+}
+
 # Apply top-level parameters
 dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
   lappend elaborate_args -G "$key=$value"