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3 changes: 1 addition & 2 deletions flow/designs/asap7/swerv_wrapper/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,7 @@ export SYNTH_KEEP_MODULES ?= \
export LIB_MODEL = CCS

export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v \
$(CLKGATE_MAP_FILE)
$(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc

export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef))
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6 changes: 6 additions & 0 deletions flow/scripts/synth_syn.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,12 @@ set elaborate_args [list \
set verilog_files [synth_verilog_files]
lappend elaborate_args {*}$verilog_files

# The platform's clock gate, as the Yosys flow reads it
# (synth_preamble.tcl)
if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } {
lappend elaborate_args $::env(CLKGATE_MAP_FILE)
}

# Apply top-level parameters
dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
lappend elaborate_args -G "$key=$value"
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