diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json deleted file mode 100644 index 8bebf70c48..0000000000 --- a/flow/scripts/variables.json +++ /dev/null @@ -1,1623 +0,0 @@ -{ - "ABC_AREA": { - "default": 0, - "description": "Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.\n", - "stages": [ - "synth" - ] - }, - "ABC_DRIVER_CELL": { - "description": "Default driver cell used during ABC synthesis.\n", - "stages": [ - "synth" - ] - }, - "ABC_LOAD_IN_FF": { - "description": "During synthesis set_load value used.\n", - "stages": [ - "synth" - ] - }, - "ABC_SCRIPT": { - "description": "Replaces the ABC script synthesis runs, so that a design can vendor and\nchange it. Ignored when SYNTH_WRAPPED_OPERATORS or SWAP_ARITH_OPERATORS\nis set: abc_new then maps each arithmetic operator with its own script.\n", - "stages": [ - "synth" - ] - }, - "ABSTRACT_SOURCE": { - "description": "Which .odb file to use to create abstract\n", - "stages": [ - "generate_abstract" - ] - }, - "ADDER_MAP_FILE": { - "description": "Optional mapping file supplied to Yosys to map adders\n", - "stages": [ - "synth" - ] - }, - "ADDITIONAL_FILES": { - "description": "Additional files to be added to `make issue` archive.\n" - }, - "ADDITIONAL_GDS": { - "description": "Hardened macro GDS files listed here.\n", - "stages": [ - "final" - ] - }, - "ADDITIONAL_LEFS": { - "description": "Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.\n" - }, - "ADDITIONAL_LIBS": { - "description": "Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.\n" - }, - "ADDITIONAL_MEMORIES": { - "description": "Experimental. Space-separated list of user-supplied `.memories` files (the memories.json JSON schema) merged onto the set AUTO_MEMORIES detects \u2014 to force-convert a memory the idiomatic gate rejects, or to describe one the scanner cannot find. See docs/user/AutoMemories.md.\n", - "stages": [ - "synth" - ] - }, - "ADDITIONAL_SITES": { - "description": "Passed as -additional_sites to initialize_floorplan.\n", - "stages": [ - "floorplan" - ] - }, - "ASAP7_USE_VT": { - "default": "RVT", - "description": "A space separated list of VT options to use with the ASAP7 standard cell library: RVT, LVT, SLVT.\n", - "stages": [ - "All stages" - ] - }, - "AUTO_MEMORIES": { - "default": 0, - "description": "Experimental. When set to 1, memories that yosys infers in the RTL (`$mem_v2` cells, module boundary only) are detected pre-synthesis, inventoried in `$(RESULTS_DIR)/memories.json`, and \u2014 when idiomatic as an SRAM macro \u2014 given generated .lib/.lef views under `$(RESULTS_DIR)/memories/`. Synthesis blackboxes those modules and all later stages read the generated views, so an existing design gets macro-based results without a memory compiler. Supported for the asap7 platform only. See docs/user/AutoMemories.md.\n" - }, - "AUTO_MEMORIES_MACRO_PLACE": { - "description": "Experimental. Space-separated list of module names of AUTO_MEMORIES_REGFILES register files to place as macros, blackboxed in synthesis and placed by the macro placer (and, in `mode netlist`, dissolved after macro placement). A register file not listed is inlined: its generated netlist of standard cells replaces the module's body in synthesis, and its cells are placed, sized and buffered with the rest of the design -- the better shape for a small design, where a macro's outline and channels cost more core than the array saves. A name no spec builds stops the build. Requires AUTO_MEMORIES=1.\n", - "stages": [ - "synth" - ] - }, - "AUTO_MEMORIES_REGFILES": { - "description": "Experimental. Space-separated list of register-file spec files, one per RTL module to build as a register file of placed standard cells rather than synthesise to flops. Each spec names its module, words, bits, read and write ports by the RTL's own port names, and the cells. memories/regfile_ram.py checks the spec against the module's ports and has OpenROAD's generate_ram build it as `_ram`, under `$(RESULTS_DIR)/memories/`, with a wrapper in the module's place. A module named in AUTO_MEMORIES_MACRO_PLACE is blackboxed like an AUTO_MEMORIES macro and placed as one; any other is inlined as its generated netlist. A placed spec in `mode netlist` then dissolves into its cells after macro placement: its core FIRM where the macro was placed, in the macro's orientation, its periphery left to placement. Every register file appears in memories.json with kind `regfile`. Requires AUTO_MEMORIES=1.\n", - "stages": [ - "synth" - ] - }, - "BALANCE_ROWS": { - "default": 0, - "description": "Balance rows during placement.\n", - "stages": [ - "place" - ] - }, - "BLOCKS": { - "description": "Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.\n", - "stages": [ - "synth" - ] - }, - "BUFFER_PORTS_ARGS": { - "description": "Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0.\n", - "stages": [ - "place" - ] - }, - "CACHED_REPORTS": { - "description": "List of pre-existing report files to copy into the reports directory before synthesis. Used when reusing prior synthesis results with SYNTH_NETLIST_FILES.\n", - "stages": [ - "synth" - ] - }, - "CAP_MARGIN": { - "description": "Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.\n", - "tunable": 1 - }, - "CDL_FILE": { - "description": "CDL master netlist file used as the -masters argument to write_cdl for generating Circuit Description Language output.\n", - "stages": [ - "final" - ] - }, - "CDL_FILES": { - "description": "Insert additional Circuit Description Language (`.cdl`) netlist files.\n" - }, - "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { - "default": 0, - "description": "Cell padding on both sides in site widths to ease routability in detail placement.\n", - "stages": [ - "floorplan", - "place", - "cts", - "grt" - ], - "tunable": 1, - "type": "int" - }, - "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { - "default": 0, - "description": "Cell padding on both sides in site widths to ease routability during global placement.\n", - "stages": [ - "place", - "floorplan" - ], - "tunable": 1, - "type": "int" - }, - "CLKGATE_MAP_FILE": { - "description": "Optional mapping file supplied to Yosys to map clock gating cells\n", - "stages": [ - "synth" - ] - }, - "CLUSTER_FLOPS": { - "default": 0, - "description": "Enable clustering of flip-flops into multi-bit flip-flops, if the platform PDK includes multi-bit flip-flops\n", - "stages": [ - "place" - ] - }, - "CLUSTER_FLOPS_ARGS": { - "default": "", - "description": "Additional arguments passed to the cluster_flops command. Only used when CLUSTER_FLOPS is set.\n", - "stages": [ - "place" - ] - }, - "CORE_AREA": { - "description": "The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).\n", - "stages": [ - "floorplan" - ], - "tunable": 1 - }, - "CORE_ASPECT_RATIO": { - "default": 1.0, - "description": "The core aspect ratio (height / width). This variable is only used when `CORE_UTILIZATION` is set.\n", - "stages": [ - "floorplan" - ], - "tunable": 1, - "type": "float" - }, - "CORE_MARGIN": { - "default": 1.0, - "description": "The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is only used when `CORE_UTILIZATION` is set.\n", - "stages": [ - "floorplan" - ], - "tunable": 1, - "type": "float" - }, - "CORE_UTILIZATION": { - "description": "The core utilization percentage (0-100).\n", - "stages": [ - "floorplan" - ], - "tunable": 1, - "type": "float" - }, - "CORNER": { - "description": "PVT corner library selection. Only available for ASAP7 and GF180 PDKs.\n" - }, - "CORNERS": { - "description": "List of timing corner names for multi-corner analysis (e.g. \"slow fast\"). When set, liberty files are loaded per corner using uppercase _LIB_FILES environment variables (e.g. corner \"slow\" reads SLOW_LIB_FILES) and timing models are generated per corner.\n", - "stages": [ - "All stages" - ] - }, - "CTS_ARGS": { - "description": "Override `clock_tree_synthesis` arguments.\n", - "stages": [ - "cts" - ] - }, - "CTS_BUF_DISTANCE": { - "description": "Distance (in microns) between buffers.\n", - "stages": [ - "cts" - ], - "tunable": 1, - "type": "float" - }, - "CTS_BUF_LIST": { - "description": "List of cells used to construct the clock tree. Overrides buffer inference.\n", - "stages": [ - "cts" - ] - }, - "CTS_CLUSTER_DIAMETER": { - "description": "Maximum diameter (in microns) of sink cluster.\n", - "stages": [ - "cts" - ], - "tunable": 1, - "type": "float" - }, - "CTS_CLUSTER_SIZE": { - "description": "Maximum number of sinks per cluster.\n", - "stages": [ - "cts" - ], - "tunable": 1, - "type": "int" - }, - "CTS_LIB_NAME": { - "description": "Name of the Liberty library to use in selecting the clock buffers.\n", - "stages": [ - "cts" - ] - }, - "CTS_SNAPSHOTS": { - "default": 0, - "description": "Create ODB/SDC files at different stages of CTS.\n", - "stages": [ - "cts" - ] - }, - "DESIGN_NAME": { - "description": "The name of the top-level module of the design.\n", - "required": true - }, - "DESIGN_NICKNAME": { - "description": "DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.\n" - }, - "DETAILED_METRICS": { - "default": 0, - "description": "If set, then calls report_metrics prior to repair operations in the CTS and global route stages\n", - "stages": [ - "cts", - "grt" - ] - }, - "DETAILED_ROUTE_ARGS": { - "description": "Add additional arguments for debugging purposes during detail route.\n", - "stages": [ - "route" - ] - }, - "DETAILED_ROUTE_END_ITERATION": { - "default": 64, - "description": "Maximum number of iterations.\n", - "stages": [ - "route" - ] - }, - "DETAIL_PLACEMENT_ARGS": { - "description": "Specify arguments to every detailed_placement call: the one in placement and the re-legalizations after clock tree synthesis, after repair in CTS and after the repairs in global route. A legalizer chosen here (-use_diamond_legalizer, -max_displacement) is therefore the one every stage uses.\n", - "stages": [ - "place", - "cts", - "grt" - ] - }, - "DFF_LIB_FILE": { - "description": "Single Liberty file for flip-flop technology mapping (dfflibmap) during synthesis. Takes precedence over DFF_MAP_FILE when set.\n", - "stages": [ - "synth" - ] - }, - "DFF_MAP_FILE": { - "description": "Optional mapping file supplied to Yosys to map D flip-flops\n", - "stages": [ - "synth" - ] - }, - "DIE_AREA": { - "description": "The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).\n", - "stages": [ - "floorplan" - ], - "tunable": 1 - }, - "DISABLE_VIA_GEN": { - "description": "Passed as -disable_via_gen to detailed_route.\n", - "stages": [ - "route" - ] - }, - "DONT_BUFFER_PORTS": { - "default": 0, - "description": "Do not buffer input/output ports during floorplanning.\n", - "stages": [ - "place" - ] - }, - "DONT_USE_CELLS": { - "description": "Dont use cells eases pin access in detailed routing.\n" - }, - "DPO_MAX_DISPLACEMENT": { - "default": "5 1", - "description": "Specifies how far an instance can be moved when optimizing.\n", - "stages": [ - "place" - ] - }, - "EARLY_SIZING_CAP_RATIO": { - "description": "Ratio between the input pin capacitance and the output pin load during initial gate sizing.\n", - "stages": [ - "place" - ] - }, - "ENABLE_DPO": { - "default": 1, - "description": "Enable detail placement with improve_placement feature.\n", - "stages": [ - "place" - ] - }, - "ENABLE_PLACE_REPAIR_TIMING": { - "default": 0, - "description": "Run repair_timing during the placement resize stage using placement parasitics. Disabled by default; pre-CTS setup/hold repair is skipped unless this is set to 1.\n", - "stages": [ - "place" - ] - }, - "ENABLE_RESISTANCE_AWARE": { - "description": "Passed as -resistance_aware to global_route.\n", - "stages": [ - "grt" - ] - }, - "FASTROUTE_TCL": { - "description": "Specifies a Tcl script with commands to run before FastRoute.\n" - }, - "FILL_CELLS": { - "description": "Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.\n", - "stages": [ - "route" - ] - }, - "FILL_CONFIG": { - "description": "JSON rule file for metal fill during chip finishing.\n" - }, - "FLOORPLAN_DEF": { - "description": "Use the DEF file to initialize floorplan. Mutually exclusive with FOOTPRINT or DIE_AREA/CORE_AREA or CORE_UTILIZATION.\n", - "stages": [ - "floorplan", - "place" - ] - }, - "FLOW_VARIANT": { - "default": "base", - "description": "Flow variant to use, used in the flow variant directory name.\n" - }, - "FOOTPRINT": { - "description": "Custom footprint definition file for ICeWall-based floorplan initialization. Mutually exclusive with FLOORPLAN_DEF or DIE_AREA/CORE_AREA or CORE_UTILIZATION.\n", - "stages": [ - "floorplan" - ] - }, - "FOOTPRINT_TCL": { - "description": "Specifies a Tcl script with custom footprint-related commands for floorplan setup.\n", - "stages": [ - "floorplan" - ] - }, - "GDS_ALLOW_EMPTY": { - "description": "Single regular expression of module names of macros that have no .gds file\n", - "stages": [ - "final" - ] - }, - "GDS_FILES": { - "description": "Path to platform GDS files.\n" - }, - "GLOBAL_CONNECT_TCL": { - "description": "File path to the add_global_connection rules that connect the supply pins of the instances to the supply nets. Sourced at floorplan right after the netlist is loaded, before any step can mark an instance dont_touch; the rules are kept in the database. The platform's file by default; a design whose PDN_TCL names other supply nets sets its own. PDN_TCL defines the grids.\n", - "stages": [ - "floorplan" - ] - }, - "GLOBAL_PLACEMENT_ARGS": { - "description": "Use additional tuning parameters during global placement other than default args defined in global_place.tcl.\n", - "stages": [ - "place" - ] - }, - "GLOBAL_ROUTE_ARGS": { - "default": "-congestion_report_iter_step 5 -verbose", - "description": "Replaces default arguments for global route. The -congestion_iterations default is set by the flow (30 for FastRoute, 10 for CUGR); add -congestion_iterations here to override it.\n", - "stages": [ - "grt" - ] - }, - "GLOBAL_ROUTE_USE_CUGR": { - "default": 0, - "description": "Passed as -use_cugr to global_route. Uses CUGR as the global routing solver instead of the default FastRoute solver. NOTE: CUGR is not ready for production.\n", - "stages": [ - "grt" - ] - }, - "GND_NETS_VOLTAGES": { - "description": "Used for IR Drop calculation.\n", - "stages": [ - "final" - ] - }, - "GPL_KEEP_OVERFLOW": { - "description": "Passed as -keep_resize_below_overflow to global_placement. Only used when GPL_TIMING_DRIVEN is enabled.\n", - "stages": [ - "place" - ] - }, - "GPL_PLACE_IOS": { - "default": 0, - "description": "Place IO pins together with the cells in global placement (-place_ios).\n", - "stages": [ - "place" - ] - }, - "GPL_RANDOM_SEED": { - "description": "Specifies a random seed for global placement. Useful for perturbation studies.\n", - "stages": [ - "place" - ] - }, - "GPL_ROUTABILITY_DRIVEN": { - "default": 1, - "description": "Specifies whether the placer should use routability driven placement.\n", - "stages": [ - "place" - ] - }, - "GPL_TIMING_DRIVEN": { - "default": 1, - "description": "Specifies whether the placer should use timing driven placement.\n", - "stages": [ - "place" - ] - }, - "GRT_SEED": { - "description": "Specifies a random seed for global routing. Useful for perturbation studies.\n", - "stages": [ - "grt" - ], - "tunable": 1, - "type": "int" - }, - "GUI_TIMING": { - "default": 1, - "description": "Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.\n" - }, - "HOLD_SLACK_MARGIN": { - "default": 0, - "description": "Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "INFER_CLKGATES": { - "default": 0, - "description": "Enables Yosys clock gate inference. By default, it uses the Liberty cell definitions to determine clock gating cell. The selection can be overridden using the POS_CLKGATE_AND_PORTS and/or NEG_CLKGATE_AND_PORTS variables.\n", - "stages": [ - "synth" - ] - }, - "IO_CONSTRAINTS": { - "description": "File path to the IO constraints .tcl file. Also used for manual placement.\n", - "stages": [ - "floorplan" - ] - }, - "IO_PLACER_H": { - "description": "A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).\n", - "stages": [ - "place" - ] - }, - "IO_PLACER_V": { - "description": "A list of metal layers on which the I/O pins are placed vertically (sides of the die).\n", - "stages": [ - "place" - ] - }, - "IR_DROP_LAYER": { - "description": "Default metal layer to report IR drop.\n" - }, - "KEEP_VARS": { - "default": 0, - "description": "Feature toggle to keep intermediate variables during the flow. This is useful for the single-run flow, where all stages of the flow are run in a single OpenROAD instance.\n", - "stages": [ - "All stages" - ] - }, - "KLAYOUT_TECH_FILE": { - "description": "A mapping from LEF/DEF to GDS using the KLayout tool.\n" - }, - "LATCH_MAP_FILE": { - "description": "Optional mapping file supplied to Yosys to map latches\n", - "stages": [ - "synth" - ] - }, - "LAYER_PARASITICS_FILE": { - "description": "Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.\n", - "type": "string" - }, - "LEC_AUX_VERILOG_FILES": { - "description": "Additional Verilog files (e.g. blackbox stubs) to include in generated netlists for formal equivalence checks.\n", - "stages": [ - "synth", - "cts", - "final" - ] - }, - "LEC_CHECK": { - "default": "$(if $(wildcard $(KEPLER_FORMAL_EXE)),1,0)", - "description": "Perform formal equivalence checks between before and after netlists. This checks CTS repair timing and the initial synthesis netlist against the final netlist. If this fails, report an issue to OpenROAD.\n", - "stages": [ - "synth", - "cts", - "final" - ] - }, - "LIB_FILES": { - "description": "A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.\n" - }, - "LIB_MODEL": { - "default": "NLDM", - "description": "Selects between NLDM and CCS timing models for the ASAP7 platform. Valid values: NLDM (default), CCS. Used in flow/platforms/asap7/config.mk to pick the LIB_DIR subdirectory and accumulate the corresponding $(CORNER)_$(LIB_MODEL)_LIB_FILES list, and in flow/scripts/load.tcl to gate CCS-specific Tcl branches.\n" - }, - "MACRO_PLACEMENT_TCL": { - "description": "Specifies the path of a TCL file on how to place macros manually.\nThe user may choose to place just some of the macros in the design.\nThe macro placer will handle the remaining unplaced macros. Note\nthat using the macro placement file generated by the macro placer\nwill not result in the same global placement as actually running\nthe macro placer: the macro placement file does not contain the\nlocations that the macro placer generates for the standard cells,\nand those locations impact global placement.\n", - "stages": [ - "floorplan" - ] - }, - "MACRO_ROWS_HALO_X": { - "description": "Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.\n", - "stages": [ - "floorplan" - ] - }, - "MACRO_ROWS_HALO_Y": { - "description": "Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.\n", - "stages": [ - "floorplan" - ] - }, - "MACRO_WRAPPERS": { - "description": "The wrapper file that replaces existing macros with their wrapped version.\n", - "stages": [ - "floorplan" - ] - }, - "MAKE_TRACKS": { - "description": "Tcl file that defines add routing tracks to a floorplan.\n", - "stages": [ - "floorplan" - ] - }, - "MATCH_CELL_FOOTPRINT": { - "default": 0, - "description": "Enforce sizing operations to only swap cells that have the same layout boundary.\n", - "stages": [ - "floorplan", - "place", - "cts", - "route" - ] - }, - "MAX_PLACE_STEP_COEF": { - "default": 1.05, - "description": "Sets the maximum phi coefficient (pcof_max / \u00b5_k Upper Bound) for global placement optimization. This parameter controls the step size upper bound in the RePlAce Nesterov optimization algorithm. Higher values allow more aggressive optimization but may risk divergence. Valid range: 1.00-1.20\n", - "stages": [ - "place" - ], - "tunable": 1, - "type": "float" - }, - "MAX_REPAIR_ANTENNAS_ITER_DRT": { - "default": 5, - "description": "Defines the maximum number of iterations post-detailed routing repair antennas will run.\n", - "stages": [ - "route" - ] - }, - "MAX_REPAIR_ANTENNAS_ITER_GRT": { - "default": 5, - "description": "Defines the maximum number of iterations post global routing repair antennas will run.\n", - "stages": [ - "grt" - ] - }, - "MAX_ROUTING_LAYER": { - "description": "The highest metal layer name to be used in routing.\n", - "stages": [ - "floorplan", - "place", - "grt", - "route", - "final" - ] - }, - "MIN_BUF_CELL_AND_PORTS": { - "description": "Used to insert a buffer cell to pass through wires. Used in synthesis.\n", - "stages": [ - "synth" - ] - }, - "MIN_CLK_ROUTING_LAYER": { - "description": "The lowest metal layer name to be used for clock-net routing in global routing. Used in flow/platforms/*/fastroute.tcl as the lower bound of `set_routing_layers -clock`. Typically higher than MIN_ROUTING_LAYER so clock nets prefer the upper, lower-RC layers. No `stages:` list because floorplan.tcl also `source`s the platform fastroute.tcl.\n" - }, - "MIN_PLACE_STEP_COEF": { - "default": 0.95, - "description": "Sets the minimum phi coefficient (pcof_min / \u00b5_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05\n", - "stages": [ - "place" - ], - "tunable": 1, - "type": "float" - }, - "MIN_ROUTING_LAYER": { - "description": "The lowest metal layer name to be used in routing.\n", - "stages": [ - "floorplan", - "place", - "grt", - "route", - "final" - ] - }, - "NEG_CLKGATE_AND_PORTS": { - "description": "Specifies the active low enable clock gating cell and port names when used in conjunction with the INFER_CLKGATES variable. Format is \"cell_name enable_port:master_clock:gated_clock\"\n", - "stages": [ - "synth" - ] - }, - "NUM_CORES": { - "description": "Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.\n", - "stages": [ - "All stages" - ] - }, - "OPENROAD_HIERARCHICAL": { - "default": 0, - "description": "Feature toggle to enable to run OpenROAD in hierarchical mode, otherwise considered flat. Will eventually be the default and this option will be retired.\n", - "stages": [ - "All stages" - ], - "tunable": 1 - }, - "OPT_POST_GRT_WNS": { - "default": 1, - "description": "Optimize WNS after global routing by additional repair_timing that uses VT swap and wire rerouting only to minimize placement and routing disturbance\n", - "stages": [ - "grt" - ] - }, - "OR_K": { - "description": "Passed as -or_k to detailed routing.\n", - "stages": [ - "route" - ] - }, - "OR_SEED": { - "description": "Passed as -or_seed to detailed routing.\n", - "stages": [ - "route" - ] - }, - "PDN_TCL": { - "description": "File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.\n", - "stages": [ - "floorplan" - ] - }, - "PLACE_DENSITY": { - "description": "The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.\n", - "stages": [ - "floorplan", - "place" - ] - }, - "PLACE_DENSITY_LB_ADDON": { - "description": "Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.\n", - "stages": [ - "floorplan", - "place" - ], - "tunable": 1, - "type": "float" - }, - "PLACE_PINS_ARGS": { - "description": "Arguments to place_pins\n", - "stages": [ - "place" - ] - }, - "PLACE_SITE": { - "description": "Placement site for core cells defined in the technology LEF file.\n", - "stages": [ - "floorplan" - ], - "tunable": 1, - "type": "string" - }, - "PLATFORM": { - "description": "Specifies process design kit or technology node to be used.\n", - "required": true - }, - "PLATFORM_TCL": { - "description": "Specifies a Tcl script with commands to run before loading design.\n" - }, - "POST_CTS_TCL": { - "description": "Specifies a Tcl script with commands to run after CTS is completed.\n", - "stages": [ - "cts" - ] - }, - "POST_DENSITY_FILL_TCL": { - "description": "Specifies a Tcl script with commands to run after density fill.\n", - "stages": [ - "final" - ] - }, - "POST_DETAIL_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run after detailed placement.\n", - "stages": [ - "place" - ] - }, - "POST_DETAIL_ROUTE_TCL": { - "description": "Specifies a Tcl script with commands to run after detailed route.\n", - "stages": [ - "route" - ] - }, - "POST_FILLCELL_TCL": { - "description": "Specifies a Tcl script with commands to run after fillcell insertion.\n", - "stages": [ - "route" - ] - }, - "POST_FINAL_REPORT_TCL": { - "description": "Specifies a Tcl script with commands to run after final report generation.\n", - "stages": [ - "final" - ] - }, - "POST_FLOORPLAN_TCL": { - "description": "Specifies a Tcl script with commands to run after floorplan is completed.\n", - "stages": [ - "floorplan" - ] - }, - "POST_GLOBAL_PLACE_SKIP_IO_TCL": { - "description": "Specifies a Tcl script with commands to run after global placement (skip IO).\n", - "stages": [ - "place" - ] - }, - "POST_GLOBAL_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run after global placement.\n", - "stages": [ - "place" - ] - }, - "POST_GLOBAL_ROUTE_TCL": { - "description": "Specifies a Tcl script with commands to run after global route.\n", - "stages": [ - "grt" - ] - }, - "POST_IO_PLACEMENT_TCL": { - "description": "Specifies a Tcl script with commands to run after IO placement.\n", - "stages": [ - "place" - ] - }, - "POST_MACRO_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run after macro placement.\n", - "stages": [ - "floorplan" - ] - }, - "POST_PDN_TCL": { - "description": "Specifies a Tcl script with commands to run after PDN generation.\n", - "stages": [ - "floorplan" - ] - }, - "POST_RESIZE_TCL": { - "description": "Specifies a Tcl script with commands to run after resize.\n", - "stages": [ - "place" - ] - }, - "POST_SYNTH_TCL": { - "description": "Specifies a Tcl script with commands to run after synthesis ODB generation.\n", - "stages": [ - "synth" - ] - }, - "POST_TAPCELL_TCL": { - "description": "Specifies a Tcl script with commands to run after tapcell.\n", - "stages": [ - "floorplan" - ] - }, - "POS_CLKGATE_AND_PORTS": { - "description": "Specifies the active high enable clock gating cell and port names when used in conjunction with the INFER_CLKGATES variable. Format is \"cell_name enable_port:master_clock:gated_clock\"\n", - "stages": [ - "synth" - ] - }, - "POWER_FILE_SCOPE": { - "description": "The SAIF or VCD scope of the current design. Typically the test bench name and design under the test instance name. Scope levels are separated with '/'.\n", - "type": "string" - }, - "PRE_CTS_TCL": { - "description": "Specifies a Tcl script with commands to run before CTS.\n", - "stages": [ - "cts" - ] - }, - "PRE_DENSITY_FILL_TCL": { - "description": "Specifies a Tcl script with commands to run before density fill.\n", - "stages": [ - "final" - ] - }, - "PRE_DETAIL_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run before detailed placement.\n", - "stages": [ - "place" - ] - }, - "PRE_DETAIL_ROUTE_TCL": { - "description": "Specifies a Tcl script with commands to run before detailed route.\n", - "stages": [ - "route" - ] - }, - "PRE_FILLCELL_TCL": { - "description": "Specifies a Tcl script with commands to run before fillcell insertion.\n", - "stages": [ - "route" - ] - }, - "PRE_FINAL_REPORT_TCL": { - "description": "Specifies a Tcl script with commands to run before final report generation.\n", - "stages": [ - "final" - ] - }, - "PRE_FLOORPLAN_TCL": { - "description": "Specifies a Tcl script with commands to run before floorplan.\n", - "stages": [ - "floorplan" - ] - }, - "PRE_GLOBAL_PLACE_SKIP_IO_TCL": { - "description": "Specifies a Tcl script with commands to run before global placement (skip IO).\n", - "stages": [ - "place" - ] - }, - "PRE_GLOBAL_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run before global placement.\n", - "stages": [ - "place" - ] - }, - "PRE_GLOBAL_ROUTE_TCL": { - "description": "Specifies a Tcl script with commands to run before global route.\n", - "stages": [ - "grt" - ] - }, - "PRE_IO_PLACEMENT_TCL": { - "description": "Specifies a Tcl script with commands to run before IO placement.\n", - "stages": [ - "place" - ] - }, - "PRE_MACRO_PLACE_TCL": { - "description": "Specifies a Tcl script with commands to run before macro placement.\n", - "stages": [ - "floorplan" - ] - }, - "PRE_PDN_TCL": { - "description": "Specifies a Tcl script with commands to run before PDN generation.\n", - "stages": [ - "floorplan" - ] - }, - "PRE_RESIZE_TCL": { - "description": "Specifies a Tcl script with commands to run before resize.\n", - "stages": [ - "place" - ] - }, - "PRE_SYNTH_TCL": { - "description": "Specifies a Tcl script with commands to run before synthesis ODB generation.\n", - "stages": [ - "synth" - ] - }, - "PRE_TAPCELL_TCL": { - "description": "Specifies a Tcl script with commands to run before tapcell.\n", - "stages": [ - "floorplan" - ] - }, - "PROCESS": { - "description": "Technology node or process in use.\n" - }, - "PWR_NETS_VOLTAGES": { - "description": "Used for IR Drop calculation.\n", - "stages": [ - "final" - ] - }, - "RCX_RULES": { - "description": "RC Extraction rules file path.\n" - }, - "RECOVER_POWER": { - "default": 0, - "description": "Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].\n" - }, - "REMOVE_CELLS_FOR_LEC": { - "description": "String patterns directly passed to write_verilog -remove_cells <> for lec checks.\n", - "type": "string" - }, - "REPAIR_PDN_VIA_LAYER": { - "description": "Remove power grid vias which generate DRC violations after detailed routing.\n" - }, - "REPORT_CLOCK_SKEW": { - "default": 1, - "description": "Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.\n", - "stages": [ - "cts", - "grt", - "route", - "final" - ] - }, - "REPORT_ENDPOINT_SLACK": { - "default": 0, - "description": "If set to 1, write the setup and hold slack of every timing endpoint at the end of every flow step (e.g. 3_3_place_gp) to $REPORTS_DIR/_endpoint_slack.json. These snapshots can be compared across steps with flow/util/endpointSlack.py. See docs/contrib/EndpointSlackTracking.md.\n", - "stages": [ - "synth", - "floorplan", - "place", - "cts", - "grt", - "route", - "final" - ] - }, - "ROUTING_LAYER_ADJUSTMENT": { - "default": 0.5, - "description": "Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/whittle.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. whittle.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.\n", - "stages": [ - "floorplan", - "place", - "grt", - "route", - "final" - ] - }, - "RTLMP_AREA_WT": { - "default": 0.1, - "description": "Weight for the area of the current floorplan.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_ARGS": { - "description": "Overrides all other RTL macro placer arguments.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_BOUNDARY_WT": { - "default": 50.0, - "description": "Weight for the boundary or how far the hard macro clusters are from boundaries.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_FENCE_LX": { - "default": 0.0, - "description": "Defines the lower left X coordinate for the global fence bounding box in microns.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_FENCE_LY": { - "default": 0.0, - "description": "Defines the lower left Y coordinate for the global fence bounding box in microns.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_FENCE_UX": { - "default": 0.0, - "description": "Defines the upper right X coordinate for the global fence bounding box in microns.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_FENCE_UY": { - "default": 0.0, - "description": "Defines the upper right Y coordinate for the global fence bounding box in microns.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_KEEP_CLUSTERING": { - "default": 0, - "description": "Set to 1 to store the RTL macro placer's clustering hierarchy in the ODB as nested dbGroups.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MAX_INST": { - "description": "Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MAX_LEVEL": { - "default": 2, - "description": "Maximum depth of the physical hierarchy tree.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MAX_MACRO": { - "description": "Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MIN_AR": { - "default": 0.33, - "description": "Specifies the minimum aspect ratio (height/width).\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MIN_CHANNEL_SIZE": { - "description": "Minimum channel width and height between macros (microns), given as one value for both, or two values \"width height\".\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MIN_INST": { - "description": "Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_MIN_MACRO": { - "description": "Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_NOTCH_WT": { - "default": 50.0, - "description": "Weight for the notch, or the existence of dead space that cannot be used for placement and routing.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_OUTLINE_WT": { - "default": 100.0, - "description": "Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_PIN_AWARE_CHANNELS": { - "default": 1, - "description": "Set to 1 to trim macro channels based on the pin locations of macros, instead of using full channels. Requires RTLMP_MIN_CHANNEL_SIZE to also be set. Defaults to 1 whenever RTLMP_MIN_CHANNEL_SIZE is set and this variable is not explicitly set to 0.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_RPT_DIR": { - "description": "Path to the directory where reports are saved.\n", - "stages": [ - "floorplan" - ] - }, - "RTLMP_WIRELENGTH_WT": { - "default": 100.0, - "description": "Weight for half-perimiter wirelength.\n", - "stages": [ - "floorplan" - ] - }, - "RUN_LOG_NAME_STEM": { - "default": "run", - "description": "Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.\n" - }, - "RUN_SCRIPT": { - "description": "Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.\n" - }, - "SAIF_FILE": { - "description": "Specifies the Switching Activity Interchange Format (SAIF) file containing pin activities and duty cycles for use in power calculation.\n", - "type": "string" - }, - "SC_LEF": { - "description": "Path to technology standard cell LEF file.\n" - }, - "SDC_FILE": { - "description": "The path to design constraint (SDC) file.\n", - "required": true, - "stages": [ - "synth" - ] - }, - "SEAL_GDS": { - "description": "Seal macro to place around the design.\n" - }, - "SEC_CHECK": { - "default": 0, - "description": "Perform a sequential equivalence check between the initial synthesis netlist and final netlist with the Kepler Formal PDR engine. If this fails, report an issue to OpenROAD.\n", - "stages": [ - "synth", - "final" - ] - }, - "SETUP_MOVE_SEQUENCE": { - "description": "Passed as -sequence to repair_timing. This should be a string of move keywords separated by commas.\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SETUP_REPAIR_PHASES": { - "description": "Passed as -phases to repair_timing. This should be a string of setup repair phase names separated by spaces. Set to PARALLEL_EVAL to repair setup timing with the experimental parallel evaluation policy. When unset, repair_timing runs its default phases.\n", - "stages": [ - "cts", - "floorplan", - "grt", - "place" - ] - }, - "SETUP_SLACK_MARGIN": { - "default": 0, - "description": "Specifies a time margin for the slack when fixing setup violations.\nThis option allows you to overfix or underfix(negative value, terminate\nretiming before 0 or positive slack).\nSee HOLD_SLACK_MARGIN for more details.\n", - "stages": [ - "cts", - "floorplan", - "grt" - ], - "tunable": 1 - }, - "SKIP_ANTENNA_REPAIR": { - "default": 0, - "description": "Skips antenna repair entirely.\n", - "stages": [ - "grt" - ] - }, - "SKIP_ANTENNA_REPAIR_POST_DRT": { - "default": 0, - "description": "Skips antenna repair post-detailed routing.\n", - "stages": [ - "route" - ] - }, - "SKIP_BUFFER_REMOVAL": { - "description": "Passed as -skip_buffer_removal to repair_timing. Do not remove buffers as a transform to fix timing violations (default: allow buffer removal).\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SKIP_CRIT_VT_SWAP": { - "description": "Do not perform VT swap on critical cells to improve QoR (default: do critical VT swap). This is an additional VT swap on critical cells that remain near the end of setup fixing. If SKIP_VT_SWAP is set to 1, this also disables critical cell VT swap.\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SKIP_CTS_REPAIR_TIMING": { - "default": 0, - "description": "Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.\n", - "stages": [ - "cts" - ] - }, - "SKIP_DETAILED_ROUTE": { - "default": 0, - "description": "Skips detailed route.\n", - "stages": [ - "route", - "final", - "generate_abstract" - ] - }, - "SKIP_FLOORPLAN_REPAIR_TIMING": { - "default": 0, - "description": "Skipping floorplan repair which sometimes does too much optimization too early.\n", - "stages": [ - "floorplan" - ] - }, - "SKIP_GATE_CLONING": { - "description": "Do not use gate cloning transform to fix timing violations (default: use gate cloning).\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SKIP_INCREMENTAL_REPAIR": { - "default": 0, - "description": "Skip incremental repair in global route.\n", - "stages": [ - "grt" - ] - }, - "SKIP_LAST_GASP": { - "description": "Do not use last gasp optimization to fix timing violations (default: use gate last gasp).\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SKIP_PIN_SWAP": { - "description": "Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SKIP_REPAIR_TIE_FANOUT": { - "default": 0, - "description": "Skip repair_tie_fanout at floorplan step.\n", - "stages": [ - "floorplan" - ] - }, - "SKIP_REPORT_METRICS": { - "default": 0, - "description": "If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.\n", - "stages": [ - "synth", - "floorplan", - "place", - "cts", - "grt", - "route", - "final" - ] - }, - "SKIP_VT_SWAP": { - "description": "Do not perform VT swap to improve QoR (default: do VT swap).\n", - "stages": [ - "cts", - "floorplan", - "grt" - ] - }, - "SLEW_MARGIN": { - "description": "Specifies a slew margin when fixing max slew violations. This option allows you to overfix.\n", - "tunable": 1 - }, - "SWAP_ARITH_OPERATORS": { - "default": 0, - "description": "Improve timing QoR by swapping ALU and MULT arithmetic operators.\n", - "stages": [ - "All stages" - ], - "tunable": 1 - }, - "SYNTH_ARGS": { - "description": "Optional synthesis variables for yosys.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_BLACKBOXES": { - "description": "List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_BLACKBOXES_FILE": { - "description": "Path to a file with more modules to treat as black boxes, one name per line, added to SYNTH_BLACKBOXES. For a parallel synthesis whose list is too long for one environment variable: Linux caps one at 128 KiB.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_CANONICALIZE_TCL": { - "description": "Specifies a Tcl script with commands to run as part of the synth canonicalize step.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_CHECKPOINT": { - "description": "Path to a Yosys RTLIL checkpoint to read in place of the default canonicalization checkpoint at the start of synth.tcl. Intended for parallel synthesis flows that reuse a checkpoint taken after coarse synthesis and `keep_hierarchy` have already been decided, so each partition skips that common prefix. Leave unset for the normal flow.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_GUT": { - "default": 0, - "description": "Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_HDL_FRONTEND": { - "description": "Select an alternative language frontend to ingest the design. Available option is \"slang\". If the variable is empty, design is read with the Yosys read_verilog command.\n", - "stages": [ - "synth" - ], - "tunable": 1 - }, - "SYNTH_HIERARCHICAL": { - "default": 0, - "description": "Enable to Synthesis hierarchically, otherwise considered flat synthesis.\n", - "stages": [ - "synth" - ], - "tunable": 1 - }, - "SYNTH_HIER_SEPARATOR": { - "default": ".", - "description": "Separator used for the synthesis flatten stage.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_INSBUF": { - "default": 1, - "description": "Insert input buffers on top-level input ports during synthesis. Useful to disable when doing parallel synthesis and concatenating netlists later as we're generating netlists of submodules.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_KEEP_MOCKED_MEMORIES": { - "default": 1, - "description": "When `SYNTH_MOCK_LARGE_MEMORIES=1`, setting this to 1, will keep mocked memories (not flattening them). This preserves some of the access logic complexity and avoids optimizations outside of the mocked memory.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_KEEP_MODULES": { - "description": "Mark modules to keep from getting removed in flattening.\nWhen the whole design is synthesized, a name that matches no module\nof the design stops synthesis. In a partition of a parallel synthesis\n(SYNTH_CHECKPOINT set) a kept module of another partition is not in\nthe partition's checkpoint, and its name is skipped.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_MEMORY_MAX_BITS": { - "default": 4096, - "description": "Maximum number of bits for memory synthesis. Ideally, real RAM or realistic fakeram should be used for RAMs much larger than 1024 bits. To temporarily ignore the RAM concerns and investigate other aspects of the design, consider setting `SYNTH_MOCK_LARGE_MEMORIES=1`, or adjusting `SYNTH_MEMORY_MAX_BITS`. ROMs, inferred memories with no write port, are not counted: a ROM holds constants that synthesis maps to logic like any other, and it goes through the normal flow. The limit is there so that a read/write memory, which belongs in a macro (`AUTO_MEMORIES`, fakeram) or a mock, does not go undetected into flip-flops; raising it to admit a large ROM would let read/write memories of that size through too.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_MINIMUM_KEEP_SIZE": { - "default": 0, - "description": "For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_MOCK_LARGE_MEMORIES": { - "default": 0, - "description": "Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. Yosys will generally infer memories from behavioral Verilog code, whether the memories are in standalone modules or instantiated within some larger module. fakeram and empty Verilog memories(blackboxes) of memories will not be inferred memories by Yosys and are therefore not affected by this variable. This is useful and convenient to separate the concern of instantiating and placing memories from investigating other issues with a design, though it comes at the expense of the increased accuracy that using realistic fakemem would provide. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues. This can be especially useful during development of designs where the behavioral model comes first and suitable memories are matched up when the design RTL is stable. A typical use case would be Chisel which will generate a behavioral model for a memories with the required clocks, ports, etc. in addition to a computer readable file with the specification of the memories that is used to [automatically](https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html/) match up suitable memory macros later in the flow. During an architectural screening study, a large range of memory configurations can be investigated quickly with this option, without getting bogged down in the concern of how to realize the memories in silicon for emphemral RTL configurations that exist only long enough to run through the ORFS flow to create a table of some characteristics of a design configuration.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_NETLIST_FILES": { - "description": "Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_OPERATIONS_ARGS": { - "description": "Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_OPT_HIER": { - "default": 0, - "description": "Optimize constants across hierarchical boundaries.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_REPEATABLE_BUILD": { - "default": 0, - "description": "License to prune anything that makes builds less repeatable, typically used with Bazel to ensure that builds are bit-for-bit identical so that caching works optimally. Removes debug information that encodes paths, timestamps, etc.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_RETIME_MODULES": { - "description": "*This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion # 8080.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_SKIP_KEEP": { - "default": 0, - "description": "Only meaningful together with SYNTH_CHECKPOINT. When set, signals that the supplied checkpoint is still canonical RTLIL (coarse synth and `keep_hierarchy` have not been run yet), so synth.tcl runs the full coarse+fine synthesis flattened. When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the checkpoint already has coarse synth + `keep_hierarchy` done and resumes from `coarse:fine`.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_SLANG_ARGS": { - "default": "", - "description": "Additional arguments passed to the slang frontend during synthesis.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_USE_SYN": { - "default": 0, - "description": "If set to 1, run synthesis using the \"syn\" tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).\n", - "stages": [ - "synth" - ] - }, - "SYNTH_VERILOG_SURGERY": { - "description": "RTL surgery as a step of the flow: a script that copies VERILOG_FILES and edits the copies before synthesis reads them, so vendored RTL stays byte-identical to upstream and the OpenROAD- and PDK-specific changes live in one script next to the design's config.mk. Typical surgery gives a memory or register file a module of its own that AUTO_MEMORIES can convert, maps a clock gate onto the platform's, rewrites a pragma for the frontend, or removes a simulation construct. A new upstream version is then a plain copy: the surgery reapplies, or stops where upstream moved. Best on generated or regular RTL (firtool, sv2v, netlists); a text edit cannot see the meaning of include files, macros, packages or `bind`. As the RTL is read (canonicalization, memory extraction, and the SYNTH_USE_SYN frontend), it runs with SYNTH_VERILOG_SURGERY_ARGS, then `--out-dir $(OBJECTS_DIR)/surgery --` and the VERILOG_FILES (by PYTHON_EXE when it ends in .py), and writes one copy per source under the same file name; synthesis reads the copies. Input file names must be unique. Diff a copy against its original to see exactly what the surgery changed. The script should fail when it does not recognise its input; a failing script, or a copy it did not write, stops synthesis.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_VERILOG_SURGERY_ARGS": { - "description": "Arguments to SYNTH_VERILOG_SURGERY, before the ones the flow adds.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_WRAPPED_ADDERS": { - "description": "Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_WRAPPED_MULTIPLIERS": { - "description": "Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.\n", - "stages": [ - "synth" - ] - }, - "SYNTH_WRAPPED_OPERATORS": { - "default": 0, - "description": "Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.\n", - "stages": [ - "All stages" - ], - "tunable": 1 - }, - "TAPCELL_TCL": { - "description": "Path to Endcap and Welltie cells file.\n", - "stages": [ - "floorplan" - ] - }, - "TAP_CELL_NAME": { - "description": "Name of the cell to use in tap cell insertion.\n" - }, - "TECH_LEF": { - "description": "A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.\n" - }, - "TIEHI_CELL_AND_PORT": { - "description": "Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.\n", - "stages": [ - "synth", - "floorplan" - ] - }, - "TIELO_CELL_AND_PORT": { - "description": "Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.\n", - "stages": [ - "synth", - "floorplan" - ] - }, - "TIE_SEPARATION": { - "default": 0, - "description": "Distance separating tie high/low instances from the load.\n", - "stages": [ - "floorplan" - ] - }, - "TNS_END_PERCENT": { - "default": 100, - "description": "Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.\n", - "stages": [ - "place", - "cts", - "floorplan", - "grt" - ] - }, - "UNSET_ABC9_BOX_CELLS": { - "description": "List of cells to unset the abc9_box attribute on\n", - "stages": [ - "synth" - ] - }, - "USE_FILL": { - "default": 0, - "description": "Whether to perform metal density filling.\n" - }, - "VCD_FILE": { - "description": "Specifies the Value Change Dump (VCD) file containing pin activities and duty cycles for use in power calculation.\n", - "type": "string" - }, - "VERILOG_DEFINES": { - "description": "Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`\n", - "stages": [ - "synth" - ] - }, - "VERILOG_FILES": { - "description": "The path to the design Verilog/SystemVerilog files providing a description of modules.\n", - "required": true, - "stages": [ - "synth" - ] - }, - "VERILOG_INCLUDE_DIRS": { - "description": "Specifies the include directories for the Verilog input files.\n", - "stages": [ - "synth" - ] - }, - "VERILOG_TOP_PARAMS": { - "description": "Apply toplevel params (if exist). Passed in as a list of key value pairs\nin tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2\n", - "stages": [ - "synth" - ] - }, - "VIA_IN_PIN_MAX_LAYER": { - "description": "Passed as -via_in_pin_top_layer to pin_access and detailed_route.\n", - "stages": [ - "grt", - "route" - ] - }, - "VIA_IN_PIN_MIN_LAYER": { - "description": "Passed as -via_in_pin_bottom_layer to pin_access and detailed_route.\n", - "stages": [ - "grt", - "route" - ] - }, - "WIRE_LOAD_MODEL": { - "description": "Name of a Liberty wire_load group applied with set_wire_load_model\nwhenever open.tcl reads timing. OpenSTA applies a wire-load model only\nto nets without parasitics, so it gives wire delay to timing read\nbefore placement and leaves placed and routed timing unaffected. An\nunknown name is an error. Empty, the default, applies none. A platform\nwhose libraries define no wire_load group can supply one in a Liberty\nfile listed in ADDITIONAL_LIBS.\n", - "type": "string" - }, - "WRITE_ODB_AND_SDC_EACH_STAGE": { - "default": 1, - "description": "Save out .sdc and .odb file after each stage, useful to disable when using a single OpenROAD instance to run all stages of the flow.\n", - "stages": [ - "All stages" - ] - }, - "YOSYS_FLAGS": { - "default": "-v 3", - "description": "Flags to pass to yosys.\n", - "stages": [ - "synth" - ] - } -}