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INFER_CLKGATES gates every group of flip-flops sharing a clock and an enable, however small, and in every module. A clock gating cell for a handful of flops costs more than the enable muxes it removes, and a module whose enable logic is timing-critical is better left ungated. INFER_CLKGATES_MIN_NET_SIZE passes -min_net_size to yosys' clockgate, so smaller groups keep their enable flip-flops. INFER_CLKGATES_EXCLUDE takes module name patterns that clockgate leaves out of its selection; only modules still present at inference (SYNTH_HIERARCHICAL, SYNTH_KEEP_MODULES) can be excluded. Both are unset by default and only take effect with INFER_CLKGATES=1. On asap7, ICG* stays in DONT_USE_CELLS unless INFER_CLKGATES=1, so the clock gating cells that inference inserts can be sized by OpenROAD. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This pull request introduces two new configuration variables, INFER_CLKGATES_EXCLUDE and INFER_CLKGATES_MIN_NET_SIZE, to allow fine-grained control over clock gating inference in Yosys. It updates the documentation, variable definitions, and synthesis scripts to support these variables. Additionally, the ASAP7 platform configuration is updated to conditionally allow the use of integrated clock gating (ICG) cells when clock gate inference is enabled. Feedback on the changes suggests a more robust way to parse the space-separated INFER_CLKGATES_EXCLUDE variable in Tcl to prevent parsing errors when patterns contain special characters like brackets.
variables.json is unused and The-OpenROAD-Project#4805 deletes it; editing it here only causes conflicts. variables.yaml carries the change. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
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INFER_CLKGATES(#4425) andPOS_CLKGATE_AND_PORTS/NEG_CLKGATE_AND_PORTS(#4448) with two controls over which flip-flops it gates.Before:
INFER_CLKGATES=1gates every group of flip-flops that share a clock and an enable, however small, in every module. A clock gating cell for a handful of flops costs more than the enable muxes it removes, and a module whose enable logic is timing-critical is better left ungated. On asap7,ICG*is always inDONT_USE_CELLS, so the ICGs that inference inserts cannot be sized by OpenROAD.Now:
INFER_CLKGATES_MIN_NET_SIZEpasses-min_net_sizeto yosys'clockgate: smaller groups keep their enable flip-flops.INFER_CLKGATES_EXCLUDEtakes yosys module name patterns thatclockgateleaves out of its selection (* <pattern> %d ...). Only modules that still exist at inference can be excluded, i.e. withSYNTH_HIERARCHICALorSYNTH_KEEP_MODULES.ICG*inDONT_USE_CELLSunlessINFER_CLKGATES=1.Both variables are unset by default and only take effect with
INFER_CLKGATES=1; a flow that sets neither is unchanged.variables.yaml,variables.jsonandFlowVariables.md(regenerated) document them.Demo,
asap7/aessynthesis (yosys 0.64), ICG instances in1_2_yosys.v:clockgatecall (liberty args omitted)INFER_CLKGATES=1clockgate+ INFER_CLKGATES_MIN_NET_SIZE=64clockgate -min_net_size 64INFER_CLKGATES=1 SYNTH_KEEP_MODULES=aes_key_expand_128clockgateaes_cipher_top+ INFER_CLKGATES_EXCLUDE=aes_key_expand_128clockgate * aes_key_expand_128 %daes_cipher_top+ INFER_CLKGATES_EXCLUDE=aes_cipher_topclockgate * aes_cipher_top %dWithout
INFER_CLKGATESthe abc call carries-dont_use ICG*as before; with it,ICG*is gone from the list.yamlfix,generate-variables-docs.py,tclintandtclfmtare clean.Open points for review:
DONT_USE_CELLStoclockgate(as before this PR); the asap7 change makes that moot there.clockgateskips flip-flops whose synchronous reset has priority over the enable, so those stay ungated. Gating them needs the reset ORed into the ICG enable, which is a yosys change, not part of this PR.🤖 Generated with Claude Code