synth: add INFER_CLKGATES_MIN_NET_SIZE and INFER_CLKGATES_EXCLUDE

docs/user/FlowVariables.md

@@ -171,6 +171,8 @@ configuration file.
 | <a name="GUI_TIMING"></a>GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1|
 | <a name="HOLD_SLACK_MARGIN"></a>HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0|
 | <a name="INFER_CLKGATES"></a>INFER_CLKGATES| Enables Yosys clock gate inference. By default, it uses the Liberty cell definitions to determine clock gating cell. The selection can be overridden using the POS_CLKGATE_AND_PORTS and/or NEG_CLKGATE_AND_PORTS variables.| 0|
+| <a name="INFER_CLKGATES_EXCLUDE"></a>INFER_CLKGATES_EXCLUDE| Space-separated Yosys module name patterns whose flip-flops INFER_CLKGATES leaves ungated, e.g. a module whose enable logic is timing-critical. Only modules that still exist at clock gate inference can be excluded, see SYNTH_HIERARCHICAL and SYNTH_KEEP_MODULES.| |
+| <a name="INFER_CLKGATES_MIN_NET_SIZE"></a>INFER_CLKGATES_MIN_NET_SIZE| Minimum number of flip-flops sharing a clock and enable for INFER_CLKGATES to replace their enable with a clock gating cell. Smaller groups keep their enable flip-flops. Unset gates every group.| |
 | <a name="IO_CONSTRAINTS"></a>IO_CONSTRAINTS| File path to the IO constraints .tcl file. Also used for manual placement.| |
 | <a name="IO_PLACER_H"></a>IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| |
 | <a name="IO_PLACER_V"></a>IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| |
@@ -362,6 +364,8 @@ configuration file.
 - [DFF_LIB_FILE](#DFF_LIB_FILE)
 - [DFF_MAP_FILE](#DFF_MAP_FILE)
 - [INFER_CLKGATES](#INFER_CLKGATES)
+- [INFER_CLKGATES_EXCLUDE](#INFER_CLKGATES_EXCLUDE)
+- [INFER_CLKGATES_MIN_NET_SIZE](#INFER_CLKGATES_MIN_NET_SIZE)
 - [LATCH_MAP_FILE](#LATCH_MAP_FILE)
 - [LEC_AUX_VERILOG_FILES](#LEC_AUX_VERILOG_FILES)
 - [LEC_CHECK](#LEC_CHECK)

flow/platforms/asap7/config.mk

@@ -22,7 +22,11 @@ export WC_VOLTAGE          = 0.63
 # Dont use cells to ease congestion
 # Specify at least one filler cell if none
 export DONT_USE_CELLS          = *x1p*_ASAP7* *xp*_ASAP7*
-export DONT_USE_CELLS          += SDF* ICG*
+export DONT_USE_CELLS          += SDF*
+# INFER_CLKGATES inserts ICG cells, which OpenROAD must then be free to size
+ifneq ($(INFER_CLKGATES),1)
+export DONT_USE_CELLS          += ICG*
+endif
 
 export SYNTH_MINIMUM_KEEP_SIZE       ?= 1000
 

flow/scripts/synth.tcl

@@ -266,6 +266,15 @@ if { [env_var_equals INFER_CLKGATES 1] } {
     # Let yosys decide on which clock gating cell to use
     lappend clkgate_args {*}$lib_args
   }
+  if { [env_var_exists_and_non_empty INFER_CLKGATES_MIN_NET_SIZE] } {
+    lappend clkgate_args -min_net_size $::env(INFER_CLKGATES_MIN_NET_SIZE)
+  }
+  if { [env_var_exists_and_non_empty INFER_CLKGATES_EXCLUDE] } {
+    lappend clkgate_args *
+    foreach pattern $::env(INFER_CLKGATES_EXCLUDE) {
+      lappend clkgate_args $pattern %d
+    }
+  }
   log_cmd clockgate {*}$clkgate_args
 }
 

flow/scripts/variables.yaml

@@ -456,6 +456,21 @@ INFER_CLKGATES:
   default: 0
   stages:
     - synth
+INFER_CLKGATES_EXCLUDE:
+  description: >
+    Space-separated Yosys module name patterns whose flip-flops
+    INFER_CLKGATES leaves ungated, e.g. a module whose enable logic is
+    timing-critical. Only modules that still exist at clock gate inference
+    can be excluded, see SYNTH_HIERARCHICAL and SYNTH_KEEP_MODULES.
+  stages:
+    - synth
+INFER_CLKGATES_MIN_NET_SIZE:
+  description: >
+    Minimum number of flip-flops sharing a clock and enable for
+    INFER_CLKGATES to replace their enable with a clock gating cell. Smaller
+    groups keep their enable flip-flops. Unset gates every group.
+  stages:
+    - synth
 NEG_CLKGATE_AND_PORTS:
   description: >
     Specifies the active low enable clock gating cell and port names when used