[oharboe]

Follow-up to #4810 and its review. blackboxes.txt had two writers and a format check in one of its three readers. It now has one writer, which writes it once, last.

Problem

• Two writers. FakeRAM's asap7 backend wrote a line per macro it built, then gen_memories.py appended a line per register-file RAM. Only the Tcl reader checked the <module> <area> format; generate_klayout_tech.py and def2stream.py take the first field of each line.
• The wrong order. FakeRAM ran before the listed register files were taken out of the inventory, so a module both idiomatic and listed in AUTO_MEMORIES_REGFILES got FakeRAM views it never uses, and blackboxes.txt still named the module with FakeRAM's area, beside its RAM when it was placed as a macro. memories.json was written twice to patch that up afterwards.

What changed

• gen_memories.py resolves the listed register files before FakeRAM runs. Their records replace the module's in memories.json, so FakeRAM, which builds views for every idiomatic record, never sees them, and memories.json has one record per module from the start. The after-the-fact rewrite is gone.
• gen_memories.py writes blackboxes.txt whole once every view exists, one <module> <area> line per macro (FakeRAM's, then the register files' RAMs) with the area its .lib states, and stops on a macro named twice. run_regfiles returns the RAMs it made instead of appending.
• FakeRAM's orfs_asap7 backend writes only the .lib/.lef views.
• util.tcl: auto_memories_areas drops its format check (the <module> <area> words are the dict), and it and auto_memories_names read through one helper, auto_memories_words. auto_memories_blackboxes moves here from synth_preamble.tcl (review nit 3).
• read_liberty.tcl: the comment says only "named by blackboxes.txt" (review nit 4).
• docs/user/AutoMemories.md: a listed module is a register file even where the idiomatic gate would convert it.

A module both idiomatic and listed in AUTO_MEMORIES_REGFILES	Before	Now
FakeRAM views (<m>.lib, <m>.lef)	written, unused	not written
blackboxes.txt, inlined	<m> <FakeRAM area>	nothing
blackboxes.txt, AUTO_MEMORIES_MACRO_PLACE	<m> <FakeRAM area> and <m>_ram <area>	<m>_ram <area>
memories.json	written, then rewritten	written once, <m> as a register file

Review nit 1 (a friendlier message when blackboxes.txt is missing) is not taken; see the reply on #4810.

Testing

• tclfmt/tclint 0.7.0 and black 26.10.1 are clean.
• flow/scripts/memories/gen_memories_test.py: new tests that a module both idiomatic and listed gets no FakeRAM views, one memories.json record as a register file and no blackboxes.txt line of its own (inlined and as a macro, generate_ram stubbed), that blackboxes.txt gives the area as the .lib states it, and that a macro named twice stops. On master the first fails (mem_128x32.lib is written) and the last has no writer to call. All 14 tests pass, as do detect_test.py, idiomatic_test.py and schema_test.py.
• tools/FakeRAM2.0/test/spsram_mask_test.py: the backend writes the views and no blackboxes.txt; fails on master, passes here. The other FakeRAM tests pass.
• flow/test/test_generate_klayout_tech.py and flow/test/test_def2stream.py pass unchanged.
• bazel-orfs test/auto_memories:am_top (hierarchical synthesis, one FakeRAM macro) built through CTS with and without this change: blackboxes.txt (am_ram_2048x32 2751.882854), memories.json, 1_2_yosys.v, 4_cts.odb and 4_cts.sdc are byte-identical. FakeRAM printed its area with %.6f and its .lib states it the same way, so the area text is unchanged.
• bazel-orfs test/regfile:regfile_top, the register-file path: placed as a macro and inlined, through floorplan, and the SYNTH_MINIMUM_KEEP_SIZE variant through synthesis. blackboxes.txt, inline.txt, regfile_cores.txt, regfiles.txt, memories.json, 1_2_yosys.v, 1_synth.odb, 2_floorplan.odb and 2_floorplan.sdc are byte-identical with and without this change, and that package's tests pass.

Not covered by a run:

• A design with a module both idiomatic and listed, the case the reordering fixes: covered by the unit test with generate_ram stubbed, not by a flow run.
• flow/test/test_auto_memories_blackboxed.py and test_auto_memories_parameters.py need a yosys with read_slang, which the local one lacks; they source only check_blackboxed.tcl and drop_parameters.tcl, which this does not touch.
• The klayout tech: the designs above stop before final; tinyRocket, tage_update and cva6 take that path in CI.

🤖 Generated with Claude Code

[gemini-code-assist]

Code Review

This pull request refactors the generation of memory lists and blackboxes in the AutoMemories flow. Specifically, it consolidates the writing of blackboxes.txt into gen_memories.py to ensure it is written once all views exist, removing this responsibility from FakeRAM generation. It also refactors register file memory handling so that listed register files are correctly recorded in memories.json and replaces duplicate logic in Tcl scripts with helper functions. Unit tests have been added to verify these changes. I have no feedback to provide as there are no review comments to evaluate.

[openroad-ci]

🔍 QoR check

Metrics reflect the PR merge build — i.e. what will land on the target branch.

Commit bc83086 · Jenkins build #1 · Baseline: build · View build on dashboard

62 design(s) checked — 0 with regression(s), 0 without a comparable baseline.