Skip to content
View amarganeshpandian's full-sized avatar

Block or report amarganeshpandian

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
amarganeshpandian/README.md

S. Amar Ganesh

Computer Science and Engineering Student
Rajalakshmi Engineering College • India

Passionate about Computer Architecture, Processor Design, Operating Systems, Digital Logic, and Embedded Systems.


About Me

I am a Computer Science and Engineering student with a strong interest in computer systems. My primary interests are computer architecture, processor microarchitecture, RTL design, and operating systems.

I enjoy understanding how computers work from the hardware level to system software by building projects, studying system fundamentals, and exploring modern processor architectures.


Areas of Interest

  • Computer Architecture
  • Processor Microarchitecture
  • RTL Design (Verilog)
  • Digital Logic Design
  • Operating Systems
  • Embedded Systems
  • Software Engineering

Currently Learning

  • RISC-V Architecture
  • Processor Microarchitecture
  • RTL Design with Verilog
  • Digital System Design
  • Operating System Internals

HDLBits Progress

I regularly solve HDLBits exercises to strengthen my understanding of digital logic and RTL design.


Languages


Tools


GitHub Stats


GitHub Streak


Contribution Graph

Activity Graph


Visitor Count


Featured Projects

Project Description
Resume Analyzer AI-powered resume analysis platform featuring resume parsing, structured analysis, resume enhancement, and ATS-oriented feedback.
Memory Management Unit (Verilog) RTL implementation of a Memory Management Unit (MMU) exploring virtual-to-physical address translation and memory management concepts.
12-bit ISA Simulator & Assembler Custom instruction set architecture simulator and assembler developed in C++, demonstrating instruction decoding, execution, and assembly translation.
1-Bit ALU using Verilog RTL implementation of a 1-bit Arithmetic Logic Unit supporting fundamental arithmetic and logical operations.

Goals

  • Strengthen my foundations in Computer Architecture and Operating Systems.
  • Build practical RTL and embedded systems projects.
  • Design processor components using Verilog.
  • Contribute to open-source systems software.
  • Explore modern processor and computer system design.

Connect


"Understanding computers from transistors to system software."

Popular repositories Loading

  1. portfolio_website portfolio_website Public

    HTML

  2. amarganeshpandian amarganeshpandian Public

  3. 1-Bit-ALU-using-verilog 1-Bit-ALU-using-verilog Public

    Verilog

  4. 12-bit-ISA-Simulator-and-Assembler 12-bit-ISA-Simulator-and-Assembler Public

    C++

  5. 240701035-CS23334--FDS-Lab 240701035-CS23334--FDS-Lab Public

  6. AmarGanesh-S-240701035-OOPS-java AmarGanesh-S-240701035-OOPS-java Public