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1. rv32-cpu rv32-cpu Public

   Single-cycle RV32I core implemented in SystemVerilog and simulated using QuestaSim.

   SystemVerilog

2. Peach-Console Peach-Console Public

   A custom FPGA-targeted 16-bit game console architecture.

   C

3. riscv-opcodes riscv-opcodes Public

   Forked from riscv/riscv-opcodes

   RISC-V Opcodes

   Python

4. onboarding-start onboarding-start Public

   Forked from UW-ASIC/onboarding-start

   Welcome to UWASIC! Start here.

   Verilog