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AVR USART Serial Communication Interface

AVR Assembly implementation of bidirectional serial communication between an ATxmega128A1U microcontroller and a PC terminal using the chip's USARTE0 peripheral at 115200 baud.

The project includes the original coursework implementation and a portfolio-refined version with bounded input handling and safer backspace behavior. The refined version was rebuilt, programmed onto the physical ATxmega128A1U board, and hardware-tested through Tera Term.

Overview

The program runs an interactive serial loop:

  1. asks whether the user wants to continue,
  2. receives keyboard input from the PC,
  3. asks for a university name and city,
  4. stores both strings in SRAM,
  5. echoes the stored strings back to the terminal,
  6. repeats until the user enters n or N.

The main engineering focus is the low-level serial I/O underneath that interaction: direct USART register configuration, byte transmit/receive routines, buffered string input, program-memory versus data-memory string handling, and defensive input handling in AVR Assembly.

Features

  • Register-level configuration of the ATxmega128A1U USARTE0 peripheral
  • 115200-baud asynchronous serial communication
  • PE2 used for RX and PE3 used for TX
  • 32 MHz internal oscillator configuration
  • Byte-level transmit and receive routines
  • Program-memory and SRAM string output
  • Buffered keyboard input with character echo
  • Backspace support
  • Uppercase/lowercase Y/N handling
  • Null-terminated SRAM strings
  • Explicit input-buffer limits in the portfolio version
  • Protection against buffer overflow
  • Protection against backspacing before the start of an empty buffer

Interface

Signal Pin Description
RXD0 PE2 Serial receive
TXD0 PE3 Serial transmit

Serial configuration: 115200 baud, 8 data bits, no parity, 1 stop bit, no flow control.

How It Works

Clock setup

The internal 32 MHz RC oscillator is enabled and selected as the system clock source before USART operation begins.

USARTE0 initialization

USARTE0 is configured for asynchronous serial communication at 115200 baud. PE3 is configured for transmit and PE2 for receive.

Byte-level I/O

putchUSARTE0 waits for the data-register-empty flag before transmitting one byte.

getchUSARTE0 waits for the receive-complete flag before returning one received byte.

Higher-level string routines are built on these two primitives.

String output

putsUSARTE0 outputs null-terminated strings from either:

  • program memory using lpm, or
  • SRAM using ld.

Buffered line input

getsUSARTE0 receives characters one at a time, echoes accepted characters to the terminal, and stores them in SRAM until Enter (0x0D) is received.

The portfolio version adds explicit buffer-length checking and prevents a backspace from moving the buffer pointer before the beginning of the allocated input buffer.

USART Routines

Routine Purpose
initUSARTE0 Initializes USARTE0 and the serial pins
putchUSARTE0 Transmits one character
putsUSARTE0 Sends a null-terminated string from flash or SRAM
getchUSARTE0 Receives one character
getsUSARTE0 Reads a bounded line into SRAM with echo/backspace handling
newline Sends carriage return and line feed
setCPUClkto32Mwith32MIntOsc Selects the 32 MHz internal oscillator

Verification

Build Verification

The portfolio version was rebuilt in Atmel Studio for the ATxmega128A1U.

The build completed successfully with 0 errors. The assembler reported three .cseg .db misalignment warnings associated with program-memory string placement; these warnings cause padding bytes and do not prevent assembly or programming.

Atmel Studio build verification

Normal Hardware Test

The refined main.asm was programmed to the physical ATxmega128A1U through the board's EDBG/PDI programming interface and tested through the EDBG Virtual COM Port in Tera Term.

The normal interaction successfully:

  • transmitted prompts from the microcontroller,
  • received y,
  • received and stored MNSU,
  • received and stored Mankato,
  • echoed both stored strings,
  • returned to the continue prompt,
  • accepted n,
  • terminated with No more.

Normal hardware verification

Edge-Case Hardware Test

The portfolio safety changes were also tested on hardware.

For the overlength-input test, more characters were typed than the destination buffer could store. The program stopped accepting additional characters at the configured limit, preserved the bounded string, continued to the next prompt, and completed the interaction normally.

The empty-buffer backspace case was also tested by pressing Backspace before entering any characters. The program remained stable and subsequently accepted normal text input, confirming that the buffer pointer did not move before the beginning of the input buffer.

Edge-case hardware verification

Portfolio Refinement

The original EE 235 implementation is preserved in:

Original/main_original.asm

The root-level main.asm retains the same USART behavior while adding:

  • clearer organization and documentation,
  • named terminal-control constants,
  • explicit maximum buffer lengths,
  • bounded SRAM writes,
  • safe handling of Backspace when the input buffer is empty.

Keeping both versions makes the distinction between the original coursework and later portfolio refinement explicit.

Repository Structure

AVR-USART-Serial-Interface/
├── README.md
├── .gitignore
├── main.asm
├── AVR USART Serial Interface.asmproj
├── AVR USART Serial Interface.componentinfo.xml
├── Original/
│   ├── main_original.asm
│   └── main_original.asmproj
└── Images/
    ├── compile_verification.png
    ├── normal_hardware_verification.png
    └── edge_case_hardware_verification.png

Tools

AVR Assembly · ATxmega128A1U · Atmel Studio · EDBG/PDI · Tera Term

What This Project Demonstrates

  • Register-level microcontroller programming
  • USART peripheral configuration
  • Serial communication at 115200 baud
  • Flash-versus-SRAM string handling
  • Buffered user input in Assembly
  • Defensive buffer-bound checking
  • Backspace edge-case handling
  • Hardware programming and serial verification

Background

This project originated in EE 235: Microprocessor Engineering Laboratory I at Minnesota State University, Mankato.

The original lab established bidirectional USART communication with a PC terminal. The portfolio version preserves that implementation while improving input safety and was subsequently rebuilt and re-verified on the physical ATxmega128A1U board.

About

AVR Assembly USART interface for the ATxmega128A1U with 115200-baud serial I/O, buffered input, backspace handling, and hardware verification.

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