The README for LAB 3 and 4 says:
LAB 3 - "This lab consists of verilog code for a single cycle implementation for ARM architecture with the following limited instruction set:"
LAB 4 - "Basic Pipelined ARM Architecture implementation"
As it says it is a "single cycle implementation for ARM architecture" or a "Basic Pipelined ARM Architecture implementation" but the instructions loaded onto instruction memory resemble MIPS ISA. Also the instruction encoding do not match any of the THUMB (16-bit) variants. There are no lw, sw, addi, subi, instructions in any of the ARM ISA. Also the register are directly referenced as R0..R31 in all ARM instructions and not as $r0..$r31. The way instructions are decoded and register are referenced, it clearly resembles a MIPS architecture.
I think the two README files should be updated to reflect the same.
The README for LAB 3 and 4 says:
LAB 3 - "This lab consists of verilog code for a single cycle implementation for ARM architecture with the following limited instruction set:"
LAB 4 - "Basic Pipelined ARM Architecture implementation"
As it says it is a "single cycle implementation for ARM architecture" or a "Basic Pipelined ARM Architecture implementation" but the instructions loaded onto instruction memory resemble MIPS ISA. Also the instruction encoding do not match any of the THUMB (16-bit) variants. There are no lw, sw, addi, subi, instructions in any of the ARM ISA. Also the register are directly referenced as R0..R31 in all ARM instructions and not as $r0..$r31. The way instructions are decoded and register are referenced, it clearly resembles a MIPS architecture.
I think the two README files should be updated to reflect the same.